Revert "[X86] Recognize POP/ADD/SUB modifying rsp in getSPAdjust. (#114265)"

This reverts commit 6fb7cdf.

Author: phoebewang

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -451,13 +451,10 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
     return -(I->getOperand(1).getImm());
   }
 
-  // Handle other opcodes we reasonably expect to see in call
-  // sequences. Note this may include spill/restore of FP/BP.
+  // Currently handle only PUSHes we can reasonably expect to see
+  // in call sequences
   switch (MI.getOpcode()) {
   default:
-    assert(!(MI.modifiesRegister(X86::RSP, &RI) ||
-             MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) &&
-           "Unhandled opcode in getSPAdjust");
     return 0;
   case X86::PUSH32r:
   case X86::PUSH32rmm:
@@ -469,30 +466,6 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
   case X86::PUSH64rmr:
   case X86::PUSH64i32:
     return 8;
-  case X86::POP32r:
-  case X86::POP32rmm:
-  case X86::POP32rmr:
-    return -4;
-  case X86::POP64r:
-  case X86::POP64rmm:
-  case X86::POP64rmr:
-    return -8;
-  // FIXME: (implement and) use isAddImmediate in the
-  // default case instead of the following ADD/SUB cases.
-  case X86::ADD32ri:
-  case X86::ADD32ri8:
-  case X86::ADD64ri32:
-    if (MI.getOperand(0).getReg() == X86::RSP &&
-        MI.getOperand(1).getReg() == X86::RSP)
-      return -MI.getOperand(2).getImm();
-    return 0;
-  case X86::SUB32ri:
-  case X86::SUB32ri8:
-  case X86::SUB64ri32:
-    if (MI.getOperand(0).getReg() == X86::RSP &&
-        MI.getOperand(1).getReg() == X86::RSP)
-      return MI.getOperand(2).getImm();
-    return 0;
   }
 }
 

llvm/lib/Target/X86/X86MachineFunctionInfo.cpp

@@ -15,9 +15,7 @@ using namespace llvm;
 
 yaml::X86MachineFunctionInfo::X86MachineFunctionInfo(
     const llvm::X86MachineFunctionInfo &MFI)
-    : AMXProgModel(MFI.getAMXProgModel()),
-      FPClobberedByCall(MFI.getFPClobberedByCall()),
-      HasPushSequences(MFI.getHasPushSequences()) {}
+    : AMXProgModel(MFI.getAMXProgModel()) {}
 
 void yaml::X86MachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
   MappingTraits<X86MachineFunctionInfo>::mapping(YamlIO, *this);
@@ -33,8 +31,6 @@ MachineFunctionInfo *X86MachineFunctionInfo::clone(
 void X86MachineFunctionInfo::initializeBaseYamlFields(
     const yaml::X86MachineFunctionInfo &YamlMFI) {
   AMXProgModel = YamlMFI.AMXProgModel;
-  FPClobberedByCall = YamlMFI.FPClobberedByCall;
-  HasPushSequences = YamlMFI.HasPushSequences;
 }
 
 void X86MachineFunctionInfo::anchor() { }

llvm/lib/Target/X86/X86MachineFunctionInfo.h

@@ -38,8 +38,6 @@ template <> struct ScalarEnumerationTraits<AMXProgModelEnum> {
 
 struct X86MachineFunctionInfo final : public yaml::MachineFunctionInfo {
   AMXProgModelEnum AMXProgModel;
-  bool FPClobberedByCall;
-  bool HasPushSequences;
 
   X86MachineFunctionInfo() = default;
   X86MachineFunctionInfo(const llvm::X86MachineFunctionInfo &MFI);
@@ -51,8 +49,6 @@ struct X86MachineFunctionInfo final : public yaml::MachineFunctionInfo {
 template <> struct MappingTraits<X86MachineFunctionInfo> {
   static void mapping(IO &YamlIO, X86MachineFunctionInfo &MFI) {
     YamlIO.mapOptional("amxProgModel", MFI.AMXProgModel);
-    YamlIO.mapOptional("FPClobberedByCall", MFI.FPClobberedByCall, false);
-    YamlIO.mapOptional("hasPushSequences", MFI.HasPushSequences, false);
   }
 };
 } // end namespace yaml