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1 parent 0dbaef6 commit 4130523Copy full SHA for 4130523
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1156,8 +1156,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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NewInfo.getAVLReg() == PrevVSETVLIMI->getOperand(0).getReg());
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// If these two VSETVLI have the same AVL and the same VLMAX,
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// we could merge these two VSETVLI.
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- if (HasSameAVL &&
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- CurInfo.getSEWLMULRatio() == NewInfo.getSEWLMULRatio()) {
+ if (HasSameAVL && CurInfo.hasSameVLMAX(NewInfo)) {
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PrevVSETVLIMI->getOperand(2).setImm(NewInfo.encodeVTYPE());
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NeedInsertVSETVLI = false;
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}
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