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[AArch64] NFC: Add RUN line for +sve2 for sve-intrinsics-perm-select.ll
The codegen for SVE and SVE2 may be different (e.g. for splice and ext). A follow-up patch will improve codegen for EXT.
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‎llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

Lines changed: 105 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE2
34

45
;
56
; CLASTA (Vectors)
@@ -570,13 +571,21 @@ define <vscale x 2 x double> @dupq_lane_f64(<vscale x 2 x double> %a, i64 %idx)
570571

571572
; NOTE: Index out of range (0-3)
572573
define <vscale x 2 x i64> @dupq_i64_range(<vscale x 2 x i64> %a) {
573-
; CHECK-LABEL: dupq_i64_range:
574-
; CHECK: // %bb.0:
575-
; CHECK-NEXT: index z1.d, #0, #1
576-
; CHECK-NEXT: and z1.d, z1.d, #0x1
577-
; CHECK-NEXT: orr z1.d, z1.d, #0x8
578-
; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d
579-
; CHECK-NEXT: ret
574+
; SVE-LABEL: dupq_i64_range:
575+
; SVE: // %bb.0:
576+
; SVE-NEXT: index z1.d, #0, #1
577+
; SVE-NEXT: and z1.d, z1.d, #0x1
578+
; SVE-NEXT: orr z1.d, z1.d, #0x8
579+
; SVE-NEXT: tbl z0.d, { z0.d }, z1.d
580+
; SVE-NEXT: ret
581+
;
582+
; SVE2-LABEL: dupq_i64_range:
583+
; SVE2: // %bb.0:
584+
; SVE2-NEXT: index z1.d, #0, #1
585+
; SVE2-NEXT: and z1.d, z1.d, #0x1
586+
; SVE2-NEXT: add z1.d, z1.d, #8 // =0x8
587+
; SVE2-NEXT: tbl z0.d, { z0.d }, z1.d
588+
; SVE2-NEXT: ret
580589
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dupq.lane.nxv2i64(<vscale x 2 x i64> %a, i64 4)
581590
ret <vscale x 2 x i64> %out
582591
}
@@ -1082,87 +1091,143 @@ define <vscale x 2 x double> @rev_f64(<vscale x 2 x double> %a) {
10821091
;
10831092

10841093
define <vscale x 16 x i8> @splice_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
1085-
; CHECK-LABEL: splice_i8:
1086-
; CHECK: // %bb.0:
1087-
; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b
1088-
; CHECK-NEXT: ret
1094+
; SVE-LABEL: splice_i8:
1095+
; SVE: // %bb.0:
1096+
; SVE-NEXT: splice z0.b, p0, z0.b, z1.b
1097+
; SVE-NEXT: ret
1098+
;
1099+
; SVE2-LABEL: splice_i8:
1100+
; SVE2: // %bb.0:
1101+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1102+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1103+
; SVE2-NEXT: splice z0.b, p0, { z0.b, z1.b }
1104+
; SVE2-NEXT: ret
10891105
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.splice.nxv16i8(<vscale x 16 x i1> %pg,
10901106
<vscale x 16 x i8> %a,
10911107
<vscale x 16 x i8> %b)
10921108
ret <vscale x 16 x i8> %out
10931109
}
10941110

10951111
define <vscale x 8 x i16> @splice_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
1096-
; CHECK-LABEL: splice_i16:
1097-
; CHECK: // %bb.0:
1098-
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
1099-
; CHECK-NEXT: ret
1112+
; SVE-LABEL: splice_i16:
1113+
; SVE: // %bb.0:
1114+
; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
1115+
; SVE-NEXT: ret
1116+
;
1117+
; SVE2-LABEL: splice_i16:
1118+
; SVE2: // %bb.0:
1119+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1120+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1121+
; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
1122+
; SVE2-NEXT: ret
11001123
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.splice.nxv8i16(<vscale x 8 x i1> %pg,
11011124
<vscale x 8 x i16> %a,
11021125
<vscale x 8 x i16> %b)
11031126
ret <vscale x 8 x i16> %out
11041127
}
11051128

11061129
define <vscale x 4 x i32> @splice_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1107-
; CHECK-LABEL: splice_i32:
1108-
; CHECK: // %bb.0:
1109-
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
1110-
; CHECK-NEXT: ret
1130+
; SVE-LABEL: splice_i32:
1131+
; SVE: // %bb.0:
1132+
; SVE-NEXT: splice z0.s, p0, z0.s, z1.s
1133+
; SVE-NEXT: ret
1134+
;
1135+
; SVE2-LABEL: splice_i32:
1136+
; SVE2: // %bb.0:
1137+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1138+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1139+
; SVE2-NEXT: splice z0.s, p0, { z0.s, z1.s }
1140+
; SVE2-NEXT: ret
11111141
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.splice.nxv4i32(<vscale x 4 x i1> %pg,
11121142
<vscale x 4 x i32> %a,
11131143
<vscale x 4 x i32> %b)
11141144
ret <vscale x 4 x i32> %out
11151145
}
11161146

11171147
define <vscale x 2 x i64> @splice_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1118-
; CHECK-LABEL: splice_i64:
1119-
; CHECK: // %bb.0:
1120-
; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
1121-
; CHECK-NEXT: ret
1148+
; SVE-LABEL: splice_i64:
1149+
; SVE: // %bb.0:
1150+
; SVE-NEXT: splice z0.d, p0, z0.d, z1.d
1151+
; SVE-NEXT: ret
1152+
;
1153+
; SVE2-LABEL: splice_i64:
1154+
; SVE2: // %bb.0:
1155+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1156+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1157+
; SVE2-NEXT: splice z0.d, p0, { z0.d, z1.d }
1158+
; SVE2-NEXT: ret
11221159
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.splice.nxv2i64(<vscale x 2 x i1> %pg,
11231160
<vscale x 2 x i64> %a,
11241161
<vscale x 2 x i64> %b)
11251162
ret <vscale x 2 x i64> %out
11261163
}
11271164

11281165
define <vscale x 8 x bfloat> @splice_bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
1129-
; CHECK-LABEL: splice_bf16:
1130-
; CHECK: // %bb.0:
1131-
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
1132-
; CHECK-NEXT: ret
1166+
; SVE-LABEL: splice_bf16:
1167+
; SVE: // %bb.0:
1168+
; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
1169+
; SVE-NEXT: ret
1170+
;
1171+
; SVE2-LABEL: splice_bf16:
1172+
; SVE2: // %bb.0:
1173+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1174+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1175+
; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
1176+
; SVE2-NEXT: ret
11331177
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.splice.nxv8bf16(<vscale x 8 x i1> %pg,
11341178
<vscale x 8 x bfloat> %a,
11351179
<vscale x 8 x bfloat> %b)
11361180
ret <vscale x 8 x bfloat> %out
11371181
}
11381182

11391183
define <vscale x 8 x half> @splice_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
1140-
; CHECK-LABEL: splice_f16:
1141-
; CHECK: // %bb.0:
1142-
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
1143-
; CHECK-NEXT: ret
1184+
; SVE-LABEL: splice_f16:
1185+
; SVE: // %bb.0:
1186+
; SVE-NEXT: splice z0.h, p0, z0.h, z1.h
1187+
; SVE-NEXT: ret
1188+
;
1189+
; SVE2-LABEL: splice_f16:
1190+
; SVE2: // %bb.0:
1191+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1192+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1193+
; SVE2-NEXT: splice z0.h, p0, { z0.h, z1.h }
1194+
; SVE2-NEXT: ret
11441195
%out = call <vscale x 8 x half> @llvm.aarch64.sve.splice.nxv8f16(<vscale x 8 x i1> %pg,
11451196
<vscale x 8 x half> %a,
11461197
<vscale x 8 x half> %b)
11471198
ret <vscale x 8 x half> %out
11481199
}
11491200

11501201
define <vscale x 4 x float> @splice_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
1151-
; CHECK-LABEL: splice_f32:
1152-
; CHECK: // %bb.0:
1153-
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
1154-
; CHECK-NEXT: ret
1202+
; SVE-LABEL: splice_f32:
1203+
; SVE: // %bb.0:
1204+
; SVE-NEXT: splice z0.s, p0, z0.s, z1.s
1205+
; SVE-NEXT: ret
1206+
;
1207+
; SVE2-LABEL: splice_f32:
1208+
; SVE2: // %bb.0:
1209+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1210+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1211+
; SVE2-NEXT: splice z0.s, p0, { z0.s, z1.s }
1212+
; SVE2-NEXT: ret
11551213
%out = call <vscale x 4 x float> @llvm.aarch64.sve.splice.nxv4f32(<vscale x 4 x i1> %pg,
11561214
<vscale x 4 x float> %a,
11571215
<vscale x 4 x float> %b)
11581216
ret <vscale x 4 x float> %out
11591217
}
11601218

11611219
define <vscale x 2 x double> @splice_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
1162-
; CHECK-LABEL: splice_f64:
1163-
; CHECK: // %bb.0:
1164-
; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
1165-
; CHECK-NEXT: ret
1220+
; SVE-LABEL: splice_f64:
1221+
; SVE: // %bb.0:
1222+
; SVE-NEXT: splice z0.d, p0, z0.d, z1.d
1223+
; SVE-NEXT: ret
1224+
;
1225+
; SVE2-LABEL: splice_f64:
1226+
; SVE2: // %bb.0:
1227+
; SVE2-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
1228+
; SVE2-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
1229+
; SVE2-NEXT: splice z0.d, p0, { z0.d, z1.d }
1230+
; SVE2-NEXT: ret
11661231
%out = call <vscale x 2 x double> @llvm.aarch64.sve.splice.nxv2f64(<vscale x 2 x i1> %pg,
11671232
<vscale x 2 x double> %a,
11681233
<vscale x 2 x double> %b)

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