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michaelmaitlandmichaelmaitland
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fixup! repond to comments
1 parent 7850ed8 commit 415eda9

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2 files changed

+20
-29
lines changed

2 files changed

+20
-29
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerLowering.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,8 @@ static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL,
7070
/// Gets the two common "VL" operands: an all-ones mask and the vector length.
7171
/// VecTy is a scalable vector type.
7272
static std::pair<MachineInstrBuilder, Register>
73-
buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB,
73+
buildDefaultVLOps(LLT VecTy, MachineIRBuilder &MIB,
7474
MachineRegisterInfo &MRI) {
75-
LLT VecTy = Dst.getLLTTy(MRI);
7675
assert(VecTy.isScalableVector() && "Expecting scalable container type");
7776
Register VL(RISCV::X0);
7877
MachineInstrBuilder Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
@@ -213,7 +212,11 @@ void lowerInsertSubvector(MachineInstr &MI, const RISCVSubtarget &STI) {
213212

214213
// We might have bitcast from a mask type: cast back to the original type if
215214
// required.
216-
MIB.buildBitcast(Dst, Inserted);
215+
if (TypeSize::isKnownLT(InterLitTy.getSizeInBits(),
216+
MRI.getType(Dst).getSizeInBits()))
217+
MIB.buildBitcast(Dst, Inserted);
218+
else
219+
Inserted->getOperand(0).setReg(Dst);
217220

218221
MI.eraseFromParent();
219222
return;

‎llvm/test/CodeGen/RISCV/GlobalISel/postlegalizer-lowering/rvv/insert-subvector.mir

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,9 @@ body: |
1919
; RV32-NEXT: [[VSCALE1:%[0-9]+]]:_(s32) = G_VSCALE i32 2
2020
; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VSCALE1]], [[VSCALE]]
2121
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEUP_VL [[ZEXT]], [[ZEXT]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s32), 0
22-
; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s8>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 4 x s8>)
2322
; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
2423
; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s8)
25-
; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[BITCAST]](<vscale x 4 x s8>), [[SPLAT_VECTOR]]
24+
; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 4 x s8>), [[SPLAT_VECTOR]]
2625
; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)
2726
; RV32-NEXT: PseudoRET implicit $v8
2827
;
@@ -34,10 +33,9 @@ body: |
3433
; RV64-NEXT: [[VSCALE1:%[0-9]+]]:_(s64) = G_VSCALE i64 2
3534
; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VSCALE1]], [[VSCALE]]
3635
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEUP_VL [[ZEXT]], [[ZEXT]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s64), 0
37-
; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s8>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 4 x s8>)
3836
; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
3937
; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s8)
40-
; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[BITCAST]](<vscale x 4 x s8>), [[SPLAT_VECTOR]]
38+
; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 4 x s8>), [[SPLAT_VECTOR]]
4139
; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)
4240
; RV64-NEXT: PseudoRET implicit $v8
4341
%0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF
@@ -60,9 +58,8 @@ body: |
6058
; RV32-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE i32 1
6159
; RV32-NEXT: [[VSCALE1:%[0-9]+]]:_(s32) = G_VSCALE i32 1
6260
; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VSCALE1]], [[VSCALE]]
63-
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s32), 0
64-
; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 1 x s8>)
65-
; RV32-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 8 x s1>)
61+
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s32), 0
62+
; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 8 x s1>)
6663
; RV32-NEXT: PseudoRET implicit $v8
6764
;
6865
; RV64-LABEL: name: insert_subvector_nxv4i1_nxv8i1
@@ -72,9 +69,8 @@ body: |
7269
; RV64-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1
7370
; RV64-NEXT: [[VSCALE1:%[0-9]+]]:_(s64) = G_VSCALE i64 1
7471
; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VSCALE1]], [[VSCALE]]
75-
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 1 x s8>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s64), 0
76-
; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 1 x s8>)
77-
; RV64-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 8 x s1>)
72+
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[ADD]](s64), 0
73+
; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 8 x s1>)
7874
; RV64-NEXT: PseudoRET implicit $v8
7975
%0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF
8076
%1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF
@@ -96,9 +92,8 @@ body: |
9692
; RV32-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE i32 8
9793
; RV32-NEXT: [[VSCALE1:%[0-9]+]]:_(s32) = G_VSCALE i32 4
9894
; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VSCALE1]], [[VSCALE]]
99-
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s32), 0
100-
; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 8 x s8>)
101-
; RV32-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 64 x s1>)
95+
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s32), 0
96+
; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 64 x s1>)
10297
; RV32-NEXT: PseudoRET implicit $v8
10398
;
10499
; RV64-LABEL: name: insert_subvector_nxv32i1_nxv64i1
@@ -108,9 +103,8 @@ body: |
108103
; RV64-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 8
109104
; RV64-NEXT: [[VSCALE1:%[0-9]+]]:_(s64) = G_VSCALE i64 4
110105
; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VSCALE1]], [[VSCALE]]
111-
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s64), 0
112-
; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 8 x s8>)
113-
; RV64-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 64 x s1>)
106+
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VSLIDEUP_VL [[DEF]], [[BITCAST]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s64), 0
107+
; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 64 x s1>)
114108
; RV64-NEXT: PseudoRET implicit $v8
115109
%0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF
116110
%1:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF
@@ -271,8 +265,7 @@ body: |
271265
; RV32-NEXT: [[VSCALE1:%[0-9]+]]:_(s32) = G_VSCALE i32 1
272266
; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VSCALE1]], [[VSCALE]]
273267
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEUP_VL [[DEF]], [[DEF]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s32), 0
274-
; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s8>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 2 x s8>)
275-
; RV32-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s8>)
268+
; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s8>)
276269
; RV32-NEXT: PseudoRET implicit $v8
277270
;
278271
; RV64-LABEL: name: insert_subvector_nxv1i8_nxv2i8
@@ -282,8 +275,7 @@ body: |
282275
; RV64-NEXT: [[VSCALE1:%[0-9]+]]:_(s64) = G_VSCALE i64 1
283276
; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VSCALE1]], [[VSCALE]]
284277
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEUP_VL [[DEF]], [[DEF]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s64), 0
285-
; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s8>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 2 x s8>)
286-
; RV64-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s8>)
278+
; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s8>)
287279
; RV64-NEXT: PseudoRET implicit $v8
288280
%0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
289281
%1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF
@@ -292,8 +284,6 @@ body: |
292284
PseudoRET implicit $v8
293285
294286
...
295-
296-
# i1-element vectors with zero index
297287
---
298288
name: insert_subvector_nxv2i16_nxv4i16
299289
legalized: true
@@ -307,8 +297,7 @@ body: |
307297
; RV32-NEXT: [[VSCALE1:%[0-9]+]]:_(s32) = G_VSCALE i32 1
308298
; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VSCALE1]], [[VSCALE]]
309299
; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEUP_VL [[DEF]], [[DEF]], [[VSCALE1]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s32), 0
310-
; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 4 x s16>)
311-
; RV32-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)
300+
; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s16>)
312301
; RV32-NEXT: PseudoRET implicit $v8
313302
;
314303
; RV64-LABEL: name: insert_subvector_nxv2i16_nxv4i16
@@ -318,8 +307,7 @@ body: |
318307
; RV64-NEXT: [[VSCALE1:%[0-9]+]]:_(s64) = G_VSCALE i64 1
319308
; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VSCALE1]], [[VSCALE]]
320309
; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEUP_VL [[DEF]], [[DEF]], [[VSCALE1]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s64), 0
321-
; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 4 x s16>)
322-
; RV64-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)
310+
; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s16>)
323311
; RV64-NEXT: PseudoRET implicit $v8
324312
%0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
325313
%1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF

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