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[AMDGPU] Change scope of resource usage info symbols such that they don't end up in the object file
1 parent f1b1c7f commit 416d3bc

14 files changed

+376
-355
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUMCResourceInfo.cpp

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "AMDGPUMCResourceInfo.h"
1616
#include "Utils/AMDGPUBaseInfo.h"
1717
#include "llvm/ADT/StringRef.h"
18+
#include "llvm/MC/MCAsmInfo.h"
1819
#include "llvm/MC/MCContext.h"
1920
#include "llvm/MC/MCSymbol.h"
2021
#include "llvm/Target/TargetMachine.h"
@@ -24,7 +25,9 @@ using namespace llvm;
2425
MCSymbol *MCResourceInfo::getSymbol(StringRef FuncName, ResourceInfoKind RIK,
2526
MCContext &OutContext) {
2627
auto GOCS = [FuncName, &OutContext](StringRef Suffix) {
27-
return OutContext.getOrCreateSymbol(FuncName + Twine(Suffix));
28+
return OutContext.getOrCreateSymbol(
29+
Twine(OutContext.getAsmInfo()->getPrivateGlobalPrefix()) + FuncName +
30+
Twine(Suffix));
2831
};
2932
switch (RIK) {
3033
case RIK_NumVGPR:
@@ -80,15 +83,21 @@ void MCResourceInfo::finalize(MCContext &OutContext) {
8083
}
8184

8285
MCSymbol *MCResourceInfo::getMaxVGPRSymbol(MCContext &OutContext) {
83-
return OutContext.getOrCreateSymbol("amdgpu.max_num_vgpr");
86+
StringRef PrivatePrefix = OutContext.getAsmInfo()->getPrivateGlobalPrefix();
87+
return OutContext.getOrCreateSymbol(Twine(PrivatePrefix) +
88+
"amdgpu.max_num_vgpr");
8489
}
8590

8691
MCSymbol *MCResourceInfo::getMaxAGPRSymbol(MCContext &OutContext) {
87-
return OutContext.getOrCreateSymbol("amdgpu.max_num_agpr");
92+
StringRef PrivatePrefix = OutContext.getAsmInfo()->getPrivateGlobalPrefix();
93+
return OutContext.getOrCreateSymbol(Twine(PrivatePrefix) +
94+
"amdgpu.max_num_agpr");
8895
}
8996

9097
MCSymbol *MCResourceInfo::getMaxSGPRSymbol(MCContext &OutContext) {
91-
return OutContext.getOrCreateSymbol("amdgpu.max_num_sgpr");
98+
StringRef PrivatePrefix = OutContext.getAsmInfo()->getPrivateGlobalPrefix();
99+
return OutContext.getOrCreateSymbol(Twine(PrivatePrefix) +
100+
"amdgpu.max_num_sgpr");
92101
}
93102

94103
void MCResourceInfo::assignResourceInfoExpr(

‎llvm/test/CodeGen/AMDGPU/agpr-register-count.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -154,28 +154,28 @@ bb:
154154
declare void @undef_func()
155155

156156
; GCN-LABEL: {{^}}kernel_call_undef_func:
157-
; GCN: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0)
158-
; GFX90A: .amdhsa_accum_offset ((((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
159-
; GCN: .set kernel_call_undef_func.num_vgpr, max(32, amdgpu.max_num_vgpr)
160-
; GCN: .set kernel_call_undef_func.num_agpr, max(0, amdgpu.max_num_agpr)
161-
; GCN: NumVgprs: kernel_call_undef_func.num_vgpr
162-
; GCN: NumAgprs: kernel_call_undef_func.num_agpr
163-
; GCN: TotalNumVgprs: totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr)
164-
; GFX908: VGPRBlocks: ((alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 4))/4)-1
165-
; GFX90A: VGPRBlocks: ((alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 8))/8)-1
166-
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0)
167-
; GFX90A: AccumOffset: ((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)+1)*4
168-
; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(kernel_call_undef_func.numbered_sgpr+(extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
169-
; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(kernel_call_undef_func.numbered_sgpr+(extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
170-
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: ((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63
157+
; GCN: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
158+
; GFX90A: .amdhsa_accum_offset ((((((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
159+
; GCN: .set .Lkernel_call_undef_func.num_vgpr, max(32, .Lamdgpu.max_num_vgpr)
160+
; GCN: .set .Lkernel_call_undef_func.num_agpr, max(0, .Lamdgpu.max_num_agpr)
161+
; GCN: NumVgprs: .Lkernel_call_undef_func.num_vgpr
162+
; GCN: NumAgprs: .Lkernel_call_undef_func.num_agpr
163+
; GCN: TotalNumVgprs: totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr)
164+
; GFX908: VGPRBlocks: ((alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 4))/4)-1
165+
; GFX90A: VGPRBlocks: ((alignto(max(max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0), 1), 8))/8)-1
166+
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0)
167+
; GFX90A: AccumOffset: ((((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4))/4)-1)+1)*4
168+
; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(.Lkernel_call_undef_func.numbered_sgpr+(extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
169+
; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(.Lkernel_call_undef_func.numbered_sgpr+(extrasgprs(.Lkernel_call_undef_func.uses_vcc, .Lkernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(.Lkernel_call_undef_func.num_agpr, .Lkernel_call_undef_func.num_vgpr), 1, 0))
170+
; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: ((((alignto(max(1, .Lkernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63
171171
define amdgpu_kernel void @kernel_call_undef_func() #0 {
172172
bb:
173173
call void @undef_func()
174174
ret void
175175
}
176176

177-
; GCN: .set amdgpu.max_num_vgpr, 32
178-
; GCN-NEXT: .set amdgpu.max_num_agpr, 32
179-
; GCN-NEXT: .set amdgpu.max_num_sgpr, 34
177+
; GCN: .set .Lamdgpu.max_num_vgpr, 32
178+
; GCN-NEXT: .set .Lamdgpu.max_num_agpr, 32
179+
; GCN-NEXT: .set .Lamdgpu.max_num_sgpr, 34
180180

181181
attributes #0 = { nounwind noinline "amdgpu-flat-work-group-size"="1,512" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }

‎llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,9 +60,9 @@ bb:
6060
declare void @undef_func()
6161

6262
; CHECK: .type kernel_call_undef_func
63-
; CHECK: .set kernel_call_undef_func.num_agpr, max(0, amdgpu.max_num_agpr)
64-
; CHECK: NumAgprs: kernel_call_undef_func.num_agpr
65-
; CHECK: .set amdgpu.max_num_agpr, 32
63+
; CHECK: .set .Lkernel_call_undef_func.num_agpr, max(0, .Lamdgpu.max_num_agpr)
64+
; CHECK: NumAgprs: .Lkernel_call_undef_func.num_agpr
65+
; CHECK: .set .Lamdgpu.max_num_agpr, 32
6666
define amdgpu_kernel void @kernel_call_undef_func() #0 {
6767
bb:
6868
call void @undef_func()

‎llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -547,20 +547,20 @@ define amdgpu_kernel void @f256() #256 {
547547
attributes #256 = { nounwind "amdgpu-flat-work-group-size"="256,256" }
548548

549549
; GCN-LABEL: {{^}}f512:
550-
; GFX9: .set f512.num_vgpr, max(128, amdgpu.max_num_vgpr)
551-
; GFX90A: .set f512.num_vgpr, max(128, amdgpu.max_num_vgpr)
552-
; GFX90A: .set f512.num_agpr, max(128, amdgpu.max_num_agpr)
553-
; GFX10WGP-WAVE32: .set f512.num_vgpr, max(256, amdgpu.max_num_vgpr)
554-
; GFX10WGP-WAVE64: .set f512.num_vgpr, max(256, amdgpu.max_num_vgpr)
555-
; GFX10CU-WAVE32: .set f512.num_vgpr, max(128, amdgpu.max_num_vgpr)
556-
; GFX10CU-WAVE64: .set f512.num_vgpr, max(128, amdgpu.max_num_vgpr)
557-
; GFX11WGP-WAVE32: .set f512.num_vgpr, max(256, amdgpu.max_num_vgpr)
558-
; GFX11WGP-WAVE64: .set f512.num_vgpr, max(256, amdgpu.max_num_vgpr)
559-
; GFX11CU-WAVE32: .set f512.num_vgpr, max(192, amdgpu.max_num_vgpr)
560-
; GFX11CU-WAVE64: .set f512.num_vgpr, max(192, amdgpu.max_num_vgpr)
561-
; GCN: NumVgprs: f512.num_vgpr
562-
; GFX90A: NumAgprs: f512.num_agpr
563-
; GFX90A: TotalNumVgprs: totalnumvgprs(f512.num_agpr, f512.num_vgpr)
550+
; GFX9: .set .Lf512.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
551+
; GFX90A: .set .Lf512.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
552+
; GFX90A: .set .Lf512.num_agpr, max(128, .Lamdgpu.max_num_agpr)
553+
; GFX10WGP-WAVE32: .set .Lf512.num_vgpr, max(256, .Lamdgpu.max_num_vgpr)
554+
; GFX10WGP-WAVE64: .set .Lf512.num_vgpr, max(256, .Lamdgpu.max_num_vgpr)
555+
; GFX10CU-WAVE32: .set .Lf512.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
556+
; GFX10CU-WAVE64: .set .Lf512.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
557+
; GFX11WGP-WAVE32: .set .Lf512.num_vgpr, max(256, .Lamdgpu.max_num_vgpr)
558+
; GFX11WGP-WAVE64: .set .Lf512.num_vgpr, max(256, .Lamdgpu.max_num_vgpr)
559+
; GFX11CU-WAVE32: .set .Lf512.num_vgpr, max(192, .Lamdgpu.max_num_vgpr)
560+
; GFX11CU-WAVE64: .set .Lf512.num_vgpr, max(192, .Lamdgpu.max_num_vgpr)
561+
; GCN: NumVgprs: .Lf512.num_vgpr
562+
; GFX90A: NumAgprs: .Lf512.num_agpr
563+
; GFX90A: TotalNumVgprs: totalnumvgprs(.Lf512.num_agpr, .Lf512.num_vgpr)
564564
define amdgpu_kernel void @f512() #512 {
565565
call void @foo()
566566
call void @use256vgprs()
@@ -569,20 +569,20 @@ define amdgpu_kernel void @f512() #512 {
569569
attributes #512 = { nounwind "amdgpu-flat-work-group-size"="512,512" }
570570

571571
; GCN-LABEL: {{^}}f1024:
572-
; GFX9: .set f1024.num_vgpr, max(64, amdgpu.max_num_vgpr)
573-
; GFX90A: .set f1024.num_vgpr, max(64, amdgpu.max_num_vgpr)
574-
; GFX90A: .set f1024.num_agpr, max(64, amdgpu.max_num_agpr)
575-
; GFX10WGP-WAVE32: .set f1024.num_vgpr, max(128, amdgpu.max_num_vgpr)
576-
; GFX10WGP-WAVE64: .set f1024.num_vgpr, max(128, amdgpu.max_num_vgpr)
577-
; GFX10CU-WAVE32: .set f1024.num_vgpr, max(64, amdgpu.max_num_vgpr)
578-
; GFX10CU-WAVE64: .set f1024.num_vgpr, max(64, amdgpu.max_num_vgpr)
579-
; GFX11WGP-WAVE32: .set f1024.num_vgpr, max(192, amdgpu.max_num_vgpr)
580-
; GFX11WGP-WAVE64: .set f1024.num_vgpr, max(192, amdgpu.max_num_vgpr)
581-
; GFX11CU-WAVE32: .set f1024.num_vgpr, max(96, amdgpu.max_num_vgpr)
582-
; GFX11CU-WAVE64: .set f1024.num_vgpr, max(96, amdgpu.max_num_vgpr)
583-
; GCN: NumVgprs: f1024.num_vgpr
584-
; GFX90A: NumAgprs: f1024.num_agpr
585-
; GFX90A: TotalNumVgprs: totalnumvgprs(f1024.num_agpr, f1024.num_vgpr)
572+
; GFX9: .set .Lf1024.num_vgpr, max(64, .Lamdgpu.max_num_vgpr)
573+
; GFX90A: .set .Lf1024.num_vgpr, max(64, .Lamdgpu.max_num_vgpr)
574+
; GFX90A: .set .Lf1024.num_agpr, max(64, .Lamdgpu.max_num_agpr)
575+
; GFX10WGP-WAVE32: .set .Lf1024.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
576+
; GFX10WGP-WAVE64: .set .Lf1024.num_vgpr, max(128, .Lamdgpu.max_num_vgpr)
577+
; GFX10CU-WAVE32: .set .Lf1024.num_vgpr, max(64, .Lamdgpu.max_num_vgpr)
578+
; GFX10CU-WAVE64: .set .Lf1024.num_vgpr, max(64, .Lamdgpu.max_num_vgpr)
579+
; GFX11WGP-WAVE32: .set .Lf1024.num_vgpr, max(192, .Lamdgpu.max_num_vgpr)
580+
; GFX11WGP-WAVE64: .set .Lf1024.num_vgpr, max(192, .Lamdgpu.max_num_vgpr)
581+
; GFX11CU-WAVE32: .set .Lf1024.num_vgpr, max(96, .Lamdgpu.max_num_vgpr)
582+
; GFX11CU-WAVE64: .set .Lf1024.num_vgpr, max(96, .Lamdgpu.max_num_vgpr)
583+
; GCN: NumVgprs: .Lf1024.num_vgpr
584+
; GFX90A: NumAgprs: .Lf1024.num_agpr
585+
; GFX90A: TotalNumVgprs: totalnumvgprs(.Lf1024.num_agpr, .Lf1024.num_vgpr)
586586
define amdgpu_kernel void @f1024() #1024 {
587587
call void @foo()
588588
call void @use256vgprs()

‎llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@
88
@alias = hidden alias void (), ptr @aliasee_default
99

1010
; ALL-LABEL: {{^}}kernel:
11-
; ALL: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel.num_agpr, kernel.num_vgpr), 1, 0)
12-
; ALL-NEXT: .amdhsa_next_free_sgpr (max(kernel.numbered_sgpr+(extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1))
13-
; GFX90A-NEXT: .amdhsa_accum_offset ((((((alignto(max(1, kernel.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
11+
; ALL: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel.num_agpr, .Lkernel.num_vgpr), 1, 0)
12+
; ALL-NEXT: .amdhsa_next_free_sgpr (max(.Lkernel.numbered_sgpr+(extrasgprs(.Lkernel.uses_vcc, .Lkernel.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(.Lkernel.uses_vcc, .Lkernel.uses_flat_scratch, 1))
13+
; GFX90A-NEXT: .amdhsa_accum_offset ((((((alignto(max(1, .Lkernel.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
1414

1515
; ALL: .set kernel.num_vgpr, max(41, aliasee_default.num_vgpr)
1616
; ALL-NEXT: .set kernel.num_agpr, max(0, aliasee_default.num_agpr)
@@ -26,9 +26,9 @@ bb:
2626
call void asm sideeffect "; clobber a26 ", "~{a26}"()
2727
ret void
2828
}
29-
; ALL: .set aliasee_default.num_vgpr, 0
30-
; ALL-NEXT: .set aliasee_default.num_agpr, 27
31-
; ALL-NEXT: .set aliasee_default.numbered_sgpr, 32
29+
; ALL: .set .Laliasee_default.num_vgpr, 0
30+
; ALL-NEXT: .set .Laliasee_default.num_agpr, 27
31+
; ALL-NEXT: .set .Laliasee_default.numbered_sgpr, 32
3232

3333
attributes #0 = { noinline norecurse nounwind optnone }
3434
attributes #1 = { noinline norecurse nounwind readnone willreturn }

‎llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ bb:
1616
ret void
1717
}
1818

19-
; CHECK: .set aliasee_default_vgpr64_sgpr102.num_vgpr, 53
20-
; CHECK-NEXT: .set aliasee_default_vgpr64_sgpr102.num_agpr, 0
21-
; CHECK-NEXT: .set aliasee_default_vgpr64_sgpr102.numbered_sgpr, 32
19+
; CHECK: .set .Laliasee_default_vgpr64_sgpr102.num_vgpr, 53
20+
; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.num_agpr, 0
21+
; CHECK-NEXT: .set .Laliasee_default_vgpr64_sgpr102.numbered_sgpr, 32
2222
define internal void @aliasee_default_vgpr64_sgpr102() #1 {
2323
bb:
2424
call void asm sideeffect "; clobber v52 ", "~{v52}"()

‎llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@
99
; The parent kernel has a higher VGPR usage than the possible callees.
1010

1111
; CHECK-LABEL: {{^}}kernel1:
12-
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel1.num_agpr, kernel1.num_vgpr), 1, 0)
13-
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel1.numbered_sgpr+(extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1))
12+
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel1.num_agpr, .Lkernel1.num_vgpr), 1, 0)
13+
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(.Lkernel1.numbered_sgpr+(extrasgprs(.Lkernel1.uses_vcc, .Lkernel1.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(.Lkernel1.uses_vcc, .Lkernel1.uses_flat_scratch, 1))
1414

1515
; CHECK: .set kernel1.num_vgpr, max(42, aliasee_vgpr32_sgpr76.num_vgpr)
1616
; CHECK-NEXT: .set kernel1.num_agpr, max(0, aliasee_vgpr32_sgpr76.num_agpr)
@@ -22,9 +22,9 @@ bb:
2222
ret void
2323
}
2424

25-
; CHECK: .set aliasee_vgpr32_sgpr76.num_vgpr, 27
26-
; CHECK-NEXT: .set aliasee_vgpr32_sgpr76.num_agpr, 0
27-
; CHECK-NEXT: .set aliasee_vgpr32_sgpr76.numbered_sgpr, 32
25+
; CHECK: .set .Laliasee_vgpr32_sgpr76.num_vgpr, 27
26+
; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.num_agpr, 0
27+
; CHECK-NEXT: .set .Laliasee_vgpr32_sgpr76.numbered_sgpr, 32
2828
define internal void @aliasee_vgpr32_sgpr76() #1 {
2929
bb:
3030
call void asm sideeffect "; clobber v26 ", "~{v26}"()

‎llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
@alias2 = hidden alias void (), ptr @aliasee_vgpr64_sgpr102
88

99
; CHECK-LABEL: {{^}}kernel2:
10-
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel2.num_agpr, kernel2.num_vgpr), 1, 0)
11-
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel2.numbered_sgpr+(extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1))
10+
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel2.num_agpr, .Lkernel2.num_vgpr), 1, 0)
11+
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(.Lkernel2.numbered_sgpr+(extrasgprs(.Lkernel2.uses_vcc, .Lkernel2.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(.Lkernel2.uses_vcc, .Lkernel2.uses_flat_scratch, 1))
1212

1313
; CHECK: .set kernel2.num_vgpr, max(41, aliasee_vgpr64_sgpr102.num_vgpr)
1414
; CHECK-NEXT: .set kernel2.num_agpr, max(0, aliasee_vgpr64_sgpr102.num_agpr)
@@ -19,9 +19,9 @@ bb:
1919
ret void
2020
}
2121

22-
; CHECK: .set aliasee_vgpr64_sgpr102.num_vgpr, 53
23-
; CHECK-NEXT: .set aliasee_vgpr64_sgpr102.num_agpr, 0
24-
; CHECK-NEXT: .set aliasee_vgpr64_sgpr102.numbered_sgpr, 32
22+
; CHECK: .set .Laliasee_vgpr64_sgpr102.num_vgpr, 53
23+
; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.num_agpr, 0
24+
; CHECK-NEXT: .set .Laliasee_vgpr64_sgpr102.numbered_sgpr, 32
2525
define internal void @aliasee_vgpr64_sgpr102() #1 {
2626
bb:
2727
call void asm sideeffect "; clobber v52 ", "~{v52}"()

‎llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
@alias3 = hidden alias void (), ptr @aliasee_vgpr256_sgpr102
88

99
; CHECK-LABEL: {{^}}kernel3:
10-
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel3.num_agpr, kernel3.num_vgpr), 1, 0)
11-
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel3.numbered_sgpr+(extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1))
10+
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(.Lkernel3.num_agpr, .Lkernel3.num_vgpr), 1, 0)
11+
; CHECK-NEXT: .amdhsa_next_free_sgpr (max(.Lkernel3.numbered_sgpr+(extrasgprs(.Lkernel3.uses_vcc, .Lkernel3.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(.Lkernel3.uses_vcc, .Lkernel3.uses_flat_scratch, 1))
1212

1313
; CHECK: .set kernel3.num_vgpr, max(41, aliasee_vgpr256_sgpr102.num_vgpr)
1414
; CHECK-NEXT: .set kernel3.num_agpr, max(0, aliasee_vgpr256_sgpr102.num_agpr)
@@ -19,9 +19,9 @@ bb:
1919
ret void
2020
}
2121

22-
; CHECK: .set aliasee_vgpr256_sgpr102.num_vgpr, 253
23-
; CHECK-NEXT: .set aliasee_vgpr256_sgpr102.num_agpr, 0
24-
; CHECK-NEXT: .set aliasee_vgpr256_sgpr102.numbered_sgpr, 33
22+
; CHECK: .set .Laliasee_vgpr256_sgpr102.num_vgpr, 253
23+
; CHECK-NEXT: .set .Laliasee_vgpr256_sgpr102.num_agpr, 0
24+
; CHECK-NEXT: .set .Laliasee_vgpr256_sgpr102.numbered_sgpr, 33
2525
define internal void @aliasee_vgpr256_sgpr102() #1 {
2626
bb:
2727
call void asm sideeffect "; clobber v252 ", "~{v252}"()

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