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[RISCV] Refactor lowerSPLAT_VECTOR_PARTS to use splatPartsI64WithVL for scalable vectors.
There was quite a bit of duplication between splatPartsI64WithVL and the scalable vector handling in lowerSPLAT_VECTOR_PARTS, but scalable vector had one additional case. Move that case to splatPartsI64WithVL which improves some fixed vector tests. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D158876
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4 files changed

+43
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 16 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -3571,6 +3571,13 @@ static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Passthru,
35713571
return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
35723572
}
35733573
}
3574+
3575+
// Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
3576+
if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
3577+
isa<ConstantSDNode>(Hi.getOperand(1)) &&
3578+
Hi.getConstantOperandVal(1) == 31)
3579+
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Lo, VL);
3580+
35743581
// If the hi bits of the splat are undefined, then it's fine to just splat Lo
35753582
// even if it might be sign extended.
35763583
if (Hi.isUndef())
@@ -6870,43 +6877,19 @@ SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
68706877
SDValue Lo = Op.getOperand(0);
68716878
SDValue Hi = Op.getOperand(1);
68726879

6873-
if (VecVT.isFixedLengthVector()) {
6874-
MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
6875-
SDLoc DL(Op);
6876-
auto VL = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).second;
6877-
6878-
SDValue Res =
6879-
splatPartsI64WithVL(DL, ContainerVT, SDValue(), Lo, Hi, VL, DAG);
6880-
return convertFromScalableVector(VecVT, Res, DAG, Subtarget);
6881-
}
6880+
MVT ContainerVT = VecVT;
6881+
if (VecVT.isFixedLengthVector())
6882+
ContainerVT = getContainerForFixedLengthVector(VecVT);
68826883

6883-
if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
6884-
int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
6885-
int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
6886-
// If Hi constant is all the same sign bit as Lo, lower this as a custom
6887-
// node in order to try and match RVV vector/scalar instructions.
6888-
if ((LoC >> 31) == HiC)
6889-
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT),
6890-
Lo, DAG.getRegister(RISCV::X0, MVT::i32));
6891-
}
6884+
auto VL = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).second;
68926885

6893-
// Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
6894-
if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
6895-
isa<ConstantSDNode>(Hi.getOperand(1)) &&
6896-
Hi.getConstantOperandVal(1) == 31)
6897-
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo,
6898-
DAG.getRegister(RISCV::X0, MVT::i32));
6886+
SDValue Res =
6887+
splatPartsI64WithVL(DL, ContainerVT, SDValue(), Lo, Hi, VL, DAG);
68996888

6900-
// If the hi bits of the splat are undefined, then it's fine to just splat Lo
6901-
// even if it might be sign extended.
6902-
if (Hi.isUndef())
6903-
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo,
6904-
DAG.getRegister(RISCV::X0, MVT::i32));
6889+
if (VecVT.isFixedLengthVector())
6890+
Res = convertFromScalableVector(VecVT, Res, DAG, Subtarget);
69056891

6906-
// Fall back to use a stack store and stride x0 vector load. Use X0 as VL.
6907-
return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT,
6908-
DAG.getUNDEF(VecVT), Lo, Hi,
6909-
DAG.getRegister(RISCV::X0, MVT::i32));
6892+
return Res;
69106893
}
69116894

69126895
// Custom-lower extensions from mask vectors by using a vselect either with 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

Lines changed: 9 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -768,17 +768,12 @@ define <4 x i32> @vwadd_vx_v4i32_i32(ptr %x, ptr %y) {
768768
define <2 x i64> @vwadd_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
769769
; RV32-LABEL: vwadd_vx_v2i64_i8:
770770
; RV32: # %bb.0:
771-
; RV32-NEXT: addi sp, sp, -16
772-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
771+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
773772
; RV32-NEXT: lb a1, 0(a1)
774773
; RV32-NEXT: vle32.v v9, (a0)
775-
; RV32-NEXT: srai a0, a1, 31
776-
; RV32-NEXT: sw a1, 8(sp)
777-
; RV32-NEXT: sw a0, 12(sp)
778-
; RV32-NEXT: addi a0, sp, 8
779-
; RV32-NEXT: vlse64.v v8, (a0), zero
774+
; RV32-NEXT: vmv.v.x v8, a1
775+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
780776
; RV32-NEXT: vwadd.wv v8, v8, v9
781-
; RV32-NEXT: addi sp, sp, 16
782777
; RV32-NEXT: ret
783778
;
784779
; RV64-LABEL: vwadd_vx_v2i64_i8:
@@ -801,17 +796,12 @@ define <2 x i64> @vwadd_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
801796
define <2 x i64> @vwadd_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
802797
; RV32-LABEL: vwadd_vx_v2i64_i16:
803798
; RV32: # %bb.0:
804-
; RV32-NEXT: addi sp, sp, -16
805-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
799+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
806800
; RV32-NEXT: lh a1, 0(a1)
807801
; RV32-NEXT: vle32.v v9, (a0)
808-
; RV32-NEXT: srai a0, a1, 31
809-
; RV32-NEXT: sw a1, 8(sp)
810-
; RV32-NEXT: sw a0, 12(sp)
811-
; RV32-NEXT: addi a0, sp, 8
812-
; RV32-NEXT: vlse64.v v8, (a0), zero
802+
; RV32-NEXT: vmv.v.x v8, a1
803+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
813804
; RV32-NEXT: vwadd.wv v8, v8, v9
814-
; RV32-NEXT: addi sp, sp, 16
815805
; RV32-NEXT: ret
816806
;
817807
; RV64-LABEL: vwadd_vx_v2i64_i16:
@@ -834,17 +824,12 @@ define <2 x i64> @vwadd_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
834824
define <2 x i64> @vwadd_vx_v2i64_i32(ptr %x, ptr %y) nounwind {
835825
; RV32-LABEL: vwadd_vx_v2i64_i32:
836826
; RV32: # %bb.0:
837-
; RV32-NEXT: addi sp, sp, -16
838-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
827+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
839828
; RV32-NEXT: lw a1, 0(a1)
840829
; RV32-NEXT: vle32.v v9, (a0)
841-
; RV32-NEXT: srai a0, a1, 31
842-
; RV32-NEXT: sw a1, 8(sp)
843-
; RV32-NEXT: sw a0, 12(sp)
844-
; RV32-NEXT: addi a0, sp, 8
845-
; RV32-NEXT: vlse64.v v8, (a0), zero
830+
; RV32-NEXT: vmv.v.x v8, a1
831+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
846832
; RV32-NEXT: vwadd.wv v8, v8, v9
847-
; RV32-NEXT: addi sp, sp, 16
848833
; RV32-NEXT: ret
849834
;
850835
; RV64-LABEL: vwadd_vx_v2i64_i32:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

Lines changed: 9 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -800,19 +800,11 @@ define <4 x i32> @vwmul_vx_v4i32_i32(ptr %x, ptr %y) {
800800
define <2 x i64> @vwmul_vx_v2i64_i8(ptr %x, ptr %y) {
801801
; RV32-LABEL: vwmul_vx_v2i64_i8:
802802
; RV32: # %bb.0:
803-
; RV32-NEXT: addi sp, sp, -16
804-
; RV32-NEXT: .cfi_def_cfa_offset 16
805803
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
806-
; RV32-NEXT: lb a1, 0(a1)
807804
; RV32-NEXT: vle32.v v8, (a0)
808-
; RV32-NEXT: srai a0, a1, 31
809-
; RV32-NEXT: sw a1, 8(sp)
810-
; RV32-NEXT: sw a0, 12(sp)
811-
; RV32-NEXT: addi a0, sp, 8
812-
; RV32-NEXT: vlse64.v v9, (a0), zero
813-
; RV32-NEXT: vsext.vf2 v10, v8
814-
; RV32-NEXT: vmul.vv v8, v9, v10
815-
; RV32-NEXT: addi sp, sp, 16
805+
; RV32-NEXT: lb a0, 0(a1)
806+
; RV32-NEXT: vsext.vf2 v9, v8
807+
; RV32-NEXT: vmul.vx v8, v9, a0
816808
; RV32-NEXT: ret
817809
;
818810
; RV64-LABEL: vwmul_vx_v2i64_i8:
@@ -835,19 +827,11 @@ define <2 x i64> @vwmul_vx_v2i64_i8(ptr %x, ptr %y) {
835827
define <2 x i64> @vwmul_vx_v2i64_i16(ptr %x, ptr %y) {
836828
; RV32-LABEL: vwmul_vx_v2i64_i16:
837829
; RV32: # %bb.0:
838-
; RV32-NEXT: addi sp, sp, -16
839-
; RV32-NEXT: .cfi_def_cfa_offset 16
840830
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
841-
; RV32-NEXT: lh a1, 0(a1)
842831
; RV32-NEXT: vle32.v v8, (a0)
843-
; RV32-NEXT: srai a0, a1, 31
844-
; RV32-NEXT: sw a1, 8(sp)
845-
; RV32-NEXT: sw a0, 12(sp)
846-
; RV32-NEXT: addi a0, sp, 8
847-
; RV32-NEXT: vlse64.v v9, (a0), zero
848-
; RV32-NEXT: vsext.vf2 v10, v8
849-
; RV32-NEXT: vmul.vv v8, v9, v10
850-
; RV32-NEXT: addi sp, sp, 16
832+
; RV32-NEXT: lh a0, 0(a1)
833+
; RV32-NEXT: vsext.vf2 v9, v8
834+
; RV32-NEXT: vmul.vx v8, v9, a0
851835
; RV32-NEXT: ret
852836
;
853837
; RV64-LABEL: vwmul_vx_v2i64_i16:
@@ -870,19 +854,11 @@ define <2 x i64> @vwmul_vx_v2i64_i16(ptr %x, ptr %y) {
870854
define <2 x i64> @vwmul_vx_v2i64_i32(ptr %x, ptr %y) {
871855
; RV32-LABEL: vwmul_vx_v2i64_i32:
872856
; RV32: # %bb.0:
873-
; RV32-NEXT: addi sp, sp, -16
874-
; RV32-NEXT: .cfi_def_cfa_offset 16
875857
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
876-
; RV32-NEXT: lw a1, 0(a1)
877858
; RV32-NEXT: vle32.v v8, (a0)
878-
; RV32-NEXT: srai a0, a1, 31
879-
; RV32-NEXT: sw a1, 8(sp)
880-
; RV32-NEXT: sw a0, 12(sp)
881-
; RV32-NEXT: addi a0, sp, 8
882-
; RV32-NEXT: vlse64.v v9, (a0), zero
883-
; RV32-NEXT: vsext.vf2 v10, v8
884-
; RV32-NEXT: vmul.vv v8, v9, v10
885-
; RV32-NEXT: addi sp, sp, 16
859+
; RV32-NEXT: lw a0, 0(a1)
860+
; RV32-NEXT: vsext.vf2 v9, v8
861+
; RV32-NEXT: vmul.vx v8, v9, a0
886862
; RV32-NEXT: ret
887863
;
888864
; RV64-LABEL: vwmul_vx_v2i64_i32:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll

Lines changed: 9 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -769,17 +769,12 @@ define <4 x i32> @vwsub_vx_v4i32_i32(ptr %x, ptr %y) {
769769
define <2 x i64> @vwsub_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
770770
; RV32-LABEL: vwsub_vx_v2i64_i8:
771771
; RV32: # %bb.0:
772-
; RV32-NEXT: addi sp, sp, -16
773-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
772+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
774773
; RV32-NEXT: lb a1, 0(a1)
775774
; RV32-NEXT: vle32.v v9, (a0)
776-
; RV32-NEXT: srai a0, a1, 31
777-
; RV32-NEXT: sw a1, 8(sp)
778-
; RV32-NEXT: sw a0, 12(sp)
779-
; RV32-NEXT: addi a0, sp, 8
780-
; RV32-NEXT: vlse64.v v8, (a0), zero
775+
; RV32-NEXT: vmv.v.x v8, a1
776+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
781777
; RV32-NEXT: vwsub.wv v8, v8, v9
782-
; RV32-NEXT: addi sp, sp, 16
783778
; RV32-NEXT: ret
784779
;
785780
; RV64-LABEL: vwsub_vx_v2i64_i8:
@@ -803,17 +798,12 @@ define <2 x i64> @vwsub_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
803798
define <2 x i64> @vwsub_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
804799
; RV32-LABEL: vwsub_vx_v2i64_i16:
805800
; RV32: # %bb.0:
806-
; RV32-NEXT: addi sp, sp, -16
807-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
801+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
808802
; RV32-NEXT: lh a1, 0(a1)
809803
; RV32-NEXT: vle32.v v9, (a0)
810-
; RV32-NEXT: srai a0, a1, 31
811-
; RV32-NEXT: sw a1, 8(sp)
812-
; RV32-NEXT: sw a0, 12(sp)
813-
; RV32-NEXT: addi a0, sp, 8
814-
; RV32-NEXT: vlse64.v v8, (a0), zero
804+
; RV32-NEXT: vmv.v.x v8, a1
805+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
815806
; RV32-NEXT: vwsub.wv v8, v8, v9
816-
; RV32-NEXT: addi sp, sp, 16
817807
; RV32-NEXT: ret
818808
;
819809
; RV64-LABEL: vwsub_vx_v2i64_i16:
@@ -837,17 +827,12 @@ define <2 x i64> @vwsub_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
837827
define <2 x i64> @vwsub_vx_v2i64_i32(ptr %x, ptr %y) nounwind {
838828
; RV32-LABEL: vwsub_vx_v2i64_i32:
839829
; RV32: # %bb.0:
840-
; RV32-NEXT: addi sp, sp, -16
841-
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
830+
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
842831
; RV32-NEXT: lw a1, 0(a1)
843832
; RV32-NEXT: vle32.v v9, (a0)
844-
; RV32-NEXT: srai a0, a1, 31
845-
; RV32-NEXT: sw a1, 8(sp)
846-
; RV32-NEXT: sw a0, 12(sp)
847-
; RV32-NEXT: addi a0, sp, 8
848-
; RV32-NEXT: vlse64.v v8, (a0), zero
833+
; RV32-NEXT: vmv.v.x v8, a1
834+
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
849835
; RV32-NEXT: vwsub.wv v8, v8, v9
850-
; RV32-NEXT: addi sp, sp, 16
851836
; RV32-NEXT: ret
852837
;
853838
; RV64-LABEL: vwsub_vx_v2i64_i32:

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