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klensy
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add more fixes
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‎clang/test/AST/ast-dump-decl.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ enum TestEnumDeclForward;
7373
// CHECK: EnumDecl{{.*}} TestEnumDeclForward
7474

7575
__module_private__ enum TestEnumDeclPrivate;
76-
// CHECK-MODULE: EnumDecl{{.*}} TestEnumDeclPrivate __module_private__
76+
// CHECK-MODULES: EnumDecl{{.*}} TestEnumDeclPrivate __module_private__
7777

7878
struct TestRecordDecl {
7979
int i;
@@ -103,7 +103,7 @@ struct TestRecordDeclForward;
103103
// CHECK: RecordDecl{{.*}} struct TestRecordDeclForward
104104

105105
__module_private__ struct TestRecordDeclPrivate;
106-
// CHECK-MODULE: RecordDecl{{.*}} struct TestRecordDeclPrivate __module_private__
106+
// CHECK-MODULES: RecordDecl{{.*}} struct TestRecordDeclPrivate __module_private__
107107

108108
enum testEnumConstantDecl {
109109
TestEnumConstantDecl,
@@ -163,7 +163,7 @@ struct testFieldDecl {
163163
// CHECK-NEXT: ConstantExpr
164164
// CHECK-NEXT: value: Int 1
165165
// CHECK-NEXT: IntegerLiteral
166-
// CHECK-MODULE: FieldDecl{{.*}} TestFieldDeclPrivate 'int' __module_private__
166+
// CHECK-MODULES: FieldDecl{{.*}} TestFieldDeclPrivate 'int' __module_private__
167167

168168
int TestVarDecl;
169169
// CHECK: VarDecl{{.*}} TestVarDecl 'int'
@@ -175,7 +175,7 @@ __thread int TestVarDeclThread;
175175
// CHECK: VarDecl{{.*}} TestVarDeclThread 'int' tls{{$}}
176176

177177
__module_private__ int TestVarDeclPrivate;
178-
// CHECK-MODULE: VarDecl{{.*}} TestVarDeclPrivate 'int' __module_private__
178+
// CHECK-MODULES: VarDecl{{.*}} TestVarDeclPrivate 'int' __module_private__
179179

180180
int TestVarDeclInit = 0;
181181
// CHECK: VarDecl{{.*}} TestVarDeclInit 'int'

‎clang/test/Analysis/cast-value-notes.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,8 @@ void evalReferences(const Shape &S) {
7777
// expected-note@-2 {{Dereference of null pointer}}
7878
// expected-warning@-3 {{Dereference of null pointer}}
7979
clang_analyzer_printState();
80-
// XX86-CHECK: "dynamic_types": [
81-
// XX86-CHECK-NEXT: { "region": "SymRegion{reg_$0<const struct clang::Shape & S>}", "dyn_type": "const class clang::Circle &", "sub_classable": true }
80+
// X86-CHECK: "dynamic_types": [
81+
// X86-CHECK-NEXT: { "region": "SymRegion{reg_$0<const Shape & S>}", "dyn_type": "const class clang::Circle &", "sub_classable": true }
8282
(void)C;
8383
}
8484
#if defined(SUPPRESSED)

‎clang/test/CodeGen/64bit-swiftcall.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1002,7 +1002,7 @@ typedef struct {
10021002
TEST(padded_alloc_size_vector)
10031003
// X86-64-LABEL: take_padded_alloc_size_vector(<3 x i32> %0, i64 %1)
10041004
// X86-64-NOT: [4 x i8]
1005-
// x86-64: ret void
1005+
// X86-64: ret void
10061006

10071007
typedef union {
10081008
float f1;

‎clang/test/CodeGen/PowerPC/builtins-ppc-altivec.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ void test1() {
535535

536536
res_vi = vec_and(vbi, vi);
537537
// CHECK: and <4 x i32>
538-
// CHECK-le: and <4 x i32>
538+
// CHECK-LE: and <4 x i32>
539539

540540
res_vi = vec_and(vi, vbi);
541541
// CHECK: and <4 x i32>

‎clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1191,7 +1191,7 @@ void test1() {
11911191
res_vsll = vec_neg(vsll);
11921192
// CHECK: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
11931193
// CHECK-LE: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
1194-
// CHECK_PPC: call to 'vec_neg' is ambiguous
1194+
// CHECK-PPC: call to 'vec_neg' is ambiguous
11951195

11961196

11971197
}

‎clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -996,30 +996,30 @@ vector bool long long test87(void) {
996996
}
997997
vector unsigned char test88(void) {
998998
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
999-
// CHECK-BE-NEXT-NEXT: ret <16 x i8>
999+
// CHECK-BE-NEXT: ret <16 x i8>
10001000
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1001-
// CHECK-NEXT-NEXT: ret <16 x i8>
1001+
// CHECK-NEXT: ret <16 x i8>
10021002
return vec_xl_len(uc,0);
10031003
}
10041004
vector signed char test89(void) {
10051005
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1006-
// CHECK-BE-NEXT-NEXT: ret <16 x i8>
1006+
// CHECK-BE-NEXT: ret <16 x i8>
10071007
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1008-
// CHECK-NEXT-NEXT: ret <16 x i8>
1008+
// CHECK-NEXT: ret <16 x i8>
10091009
return vec_xl_len(sc,0);
10101010
}
10111011
vector unsigned short test90(void) {
10121012
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1013-
// CHECK-BE-NEXT-NEXT: ret <8 x i16>
1013+
// CHECK-BE-NEXT: ret <8 x i16>
10141014
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1015-
// CHECK-NEXT-NEXT: ret <8 x i16>
1015+
// CHECK-NEXT: ret <8 x i16>
10161016
return vec_xl_len(us,0);
10171017
}
10181018
vector signed short test91(void) {
10191019
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1020-
// CHECK-BE-NEXT-NEXT: ret <8 x i16>
1020+
// CHECK-BE-NEXT: ret <8 x i16>
10211021
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1022-
// CHECK-NEXT-NEXT: ret <8 x i16>
1022+
// CHECK-NEXT: ret <8 x i16>
10231023
return vec_xl_len(ss,0);
10241024
}
10251025
vector unsigned int test92(void) {
@@ -1040,49 +1040,49 @@ vector signed int test93(void) {
10401040

10411041
vector float test94(void) {
10421042
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1043-
// CHECK-BE-NEXT-NEXT: ret <4 x i32>
1043+
// CHECK-BE-NEXT: ret <4 x i32>
10441044
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1045-
// CHECK-NEXT-NEXT: ret <4 x i32>
1045+
// CHECK-NEXT: ret <4 x i32>
10461046
return vec_xl_len(f,0);
10471047
}
10481048

10491049
vector unsigned long long test95(void) {
10501050
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1051-
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1051+
// CHECK-BE-NEXT: ret <2 x i64>
10521052
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1053-
// CHECK-NEXT-NEXT: ret <2 x i64>
1053+
// CHECK-NEXT: ret <2 x i64>
10541054
return vec_xl_len(ull,0);
10551055
}
10561056

10571057
vector signed long long test96(void) {
10581058
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1059-
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1059+
// CHECK-BE-NEXT: ret <2 x i64>
10601060
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1061-
// CHECK-NEXT-NEXT: ret <2 x i64>
1061+
// CHECK-NEXT: ret <2 x i64>
10621062
return vec_xl_len(sll,0);
10631063
}
10641064

10651065
vector double test97(void) {
10661066
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1067-
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1067+
// CHECK-BE-NEXT: ret <2 x i64>
10681068
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1069-
// CHECK-NEXT-NEXT: ret <2 x i64>
1069+
// CHECK-NEXT: ret <2 x i64>
10701070
return vec_xl_len(d,0);
10711071
}
10721072

10731073
vector unsigned __int128 test98(void) {
10741074
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1075-
// CHECK-BE-NEXT-NEXT: ret <1 x i128>
1075+
// CHECK-BE-NEXT: ret <1 x i128>
10761076
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1077-
// CHECK-NEXT-NEXT: ret <1 x i128>
1077+
// CHECK-NEXT: ret <1 x i128>
10781078
return vec_xl_len(uint128,0);
10791079
}
10801080

10811081
vector signed __int128 test99(void) {
10821082
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1083-
// CHECK-BE-NEXT-NEXT: ret <1 x i128>
1083+
// CHECK-BE-NEXT: ret <1 x i128>
10841084
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
1085-
// CHECK-NEXT-NEXT: ret <1 x i128>
1085+
// CHECK-NEXT: ret <1 x i128>
10861086
return vec_xl_len(sint128,0);
10871087
}
10881088

‎clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -69,12 +69,12 @@ void test1() {
6969
res_vlll = vec_addc(vlll, vlll);
7070
// CHECK: @llvm.ppc.altivec.vaddcuq
7171
// CHECK-LE: @llvm.ppc.altivec.vaddcuq
72-
// KCHECK-PPC: error: call to 'vec_addc' is ambiguous
72+
// CHECK-PPC: error: call to 'vec_addc' is ambiguous
7373

7474
res_vulll = vec_addc(vulll, vulll);
7575
// CHECK: @llvm.ppc.altivec.vaddcuq
7676
// CHECK-LE: @llvm.ppc.altivec.vaddcuq
77-
// KCHECK-PPC: error: call to 'vec_addc' is ambiguous
77+
// CHECK-PPC: error: call to 'vec_addc' is ambiguous
7878

7979

8080
/* vec_vaddcuq */
@@ -165,12 +165,12 @@ void test1() {
165165
res_vlll = vec_subc(vlll, vlll);
166166
// CHECK: @llvm.ppc.altivec.vsubcuq
167167
// CHECK-LE: @llvm.ppc.altivec.vsubcuq
168-
// KCHECK-PPC: error: call to 'vec_subc' is ambiguous
168+
// CHECK-PPC: error: call to 'vec_subc' is ambiguous
169169

170170
res_vulll = vec_subc(vulll, vulll);
171171
// CHECK: @llvm.ppc.altivec.vsubcuq
172172
// CHECK-LE: @llvm.ppc.altivec.vsubcuq
173-
// KCHECK-PPC: error: call to 'vec_subc' is ambiguous
173+
// CHECK-PPC: error: call to 'vec_subc' is ambiguous
174174

175175
res_vuc = vec_subc_u128(vuc, vuc);
176176
// CHECK: @llvm.ppc.altivec.vsubcuq
@@ -219,7 +219,7 @@ void test1() {
219219
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, ptr {{%.+}}, align 16
220220
// CHECK-LE: xor <16 x i8>
221221
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
222-
// CHECK_PPC: error: call to 'vec_revb' is ambiguous
222+
// CHECK-PPC: error: call to 'vec_revb' is ambiguous
223223

224224
/* vec_xl */
225225
res_vlll = vec_xl(param_sll, &param_lll);

‎clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -153,10 +153,10 @@ bfloat16x4_t test_vreinterpret_bf16_p64(poly64x1_t a) { return vreinterpret_bf
153153
bfloat16x8_t test_vreinterpretq_bf16_p64(poly64x2_t a) { return vreinterpretq_bf16_p64(a); }
154154

155155
// TODO: poly128_t not implemented on aarch32
156-
// CHCK-LABEL: @test_vreinterpretq_bf16_p128(
157-
// CHCK-NEXT: entry:
158-
// CHCK-NEXT: [[TMP0:%.*]] = bitcast i128 [[A:%.*]] to <4 x i32>
159-
// CHCK-NEXT: ret <4 x i32> [[TMP0]]
156+
// COM: CHECK-LABEL: @test_vreinterpretq_bf16_p128(
157+
// COM: CHECK-NEXT: entry:
158+
// COM: CHECK-NEXT: [[TMP0:%.*]] = bitcast i128 [[A:%.*]] to <4 x i32>
159+
// COM: CHECK-NEXT: ret <4 x i32> [[TMP0]]
160160
//
161161
//bfloat16x8_t test_vreinterpretq_bf16_p128(poly128_t a) { return vreinterpretq_bf16_p128(a); }
162162

@@ -306,9 +306,9 @@ int64x2_t test_vreinterpretq_s64_bf16(bfloat16x8_t a) { return vreinterpretq_
306306
poly64x2_t test_vreinterpretq_p64_bf16(bfloat16x8_t a) { return vreinterpretq_p64_bf16(a); }
307307

308308
// TODO: poly128_t not implemented on aarch32
309-
// CHCK-LABEL: @test_vreinterpretq_p128_bf16(
310-
// CHCK-NEXT: entry:
311-
// CHCK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
312-
// CHCK-NEXT: ret i128 [[TMP0]]
309+
// COM: CHECK-LABEL: @test_vreinterpretq_p128_bf16(
310+
// COM: CHECK-NEXT: entry:
311+
// COM: CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
312+
// COM: CHECK-NEXT: ret i128 [[TMP0]]
313313
//
314314
//poly128_t test_vreinterpretq_p128_bf16(bfloat16x8_t a) { return vreinterpretq_p128_bf16(a); }

‎clang/test/CodeGen/arm-metadata.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,5 @@
88
// SHORT-WCHAR: !{{[0-9]+}} = !{i32 1, !"wchar_size", i32 2}
99
// SHORT-WCHAR: !{{[0-9]+}} = !{i32 1, !"min_enum_size", i32 4}
1010

11-
// SHORT_ENUM: !{{[0-9]+}} = !{i32 1, !"wchar_size", i32 4}
11+
// SHORT-ENUM: !{{[0-9]+}} = !{i32 1, !"wchar_size", i32 4}
1212
// SHORT-ENUM: !{{[0-9]+}} = !{i32 1, !"min_enum_size", i32 1}

‎clang/test/CodeGen/arm-poly-add.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -74,13 +74,13 @@ poly64x2_t test_vaddq_p64(poly64x2_t a, poly64x2_t b){
7474
}
7575

7676
// TODO: poly128_t not implemented on aarch32
77-
// CHCK-LABEL: @test_vaddq_p128(
78-
// CHCK-NEXT: entry:
79-
// CHCK-NEXT: [[TMP0:%.*]] = bitcast i128 [[A:%.*]] to <16 x i8>
80-
// CHCK-NEXT: [[TMP1:%.*]] = bitcast i128 [[B:%.*]] to <16 x i8>
81-
// CHCK-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
82-
// CHCK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to i128
83-
// CHCK-NEXT: ret i128 [[TMP3]]
77+
// COM: CHECK-LABEL: @test_vaddq_p128(
78+
// COM: CHECK-NEXT: entry:
79+
// COM: CHECK-NEXT: [[TMP0:%.*]] = bitcast i128 [[A:%.*]] to <16 x i8>
80+
// COM: CHECK-NEXT: [[TMP1:%.*]] = bitcast i128 [[B:%.*]] to <16 x i8>
81+
// COM: CHECK-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
82+
// COM: CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to i128
83+
// COM: CHECK-NEXT: ret i128 [[TMP3]]
8484
//
8585
//poly128_t test_vaddq_p128 (poly128_t a, poly128_t b){
8686
// return vaddq_p128(a, b);

‎clang/test/CodeGen/attr-mustprogress.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ int b = 0;
3030
// CHECK: for.cond:
3131
// C99-NOT: br {{.*}}!llvm.loop
3232
// C11-NOT: br {{.*}}!llvm.loop
33-
// FINITE-NOR: br {{.*}}!llvm.loop
33+
// FINITE-NOT: br {{.*}}!llvm.loop
3434
//
3535
void f0(void) {
3636
for (; ;) ;

‎clang/test/CodeGen/debug-info-macro.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// This test checks that macro Debug info is correctly generated.
1111

1212
// TODO: Check for an following entry once support macros defined in pch files.
13-
// -PCH: !DIMacro(type: DW_MACINFO_define, name: "C3", value: "1")>
13+
// COM: PCH: !DIMacro(type: DW_MACINFO_define, name: "C3", value: "1")>
1414

1515
#line 15
1616
/*Line 15*/ #define D1 1

‎clang/test/CodeGen/ffp-contract-option.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,8 @@ float mymuladd(float x, float y, float z) {
112112
// CHECK-FPC-OFF: load float, ptr
113113
// CHECK-FPC-OFF: fadd float {{.*}}, {{.*}}
114114

115-
// CHECK-FFPC-OFF: load float, ptr
116-
// CHECK-FFPC-OFF: load float, ptr
115+
// CHECK-FPSC-OFF: load float, ptr
116+
// CHECK-FPSC-OFF: load float, ptr
117117
// CHECK-FPSC-OFF: call float @llvm.experimental.constrained.fmul.f32(float {{.*}}, float {{.*}}, {{.*}})
118118
// CHECK-FPSC-OFF: load float, ptr
119119
// CHECK-FPSC-OFF: [[RES:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, {{.*}})

‎clang/test/CodeGen/fp16-ops-strictfp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -502,7 +502,7 @@ void foo(void) {
502502

503503
// Check assignments (inc. compound)
504504
// CHECK: store {{.*}} half {{.*}}, ptr
505-
// xATIVE-HALF: store {{.*}} half 0xHC000 // FIXME: We should be folding here.
505+
// COM: NATIVE-HALF: store {{.*}} half 0xHC000 // FIXME: We should be folding here.
506506
h0 = h1;
507507

508508
// CHECK: call half @llvm.experimental.constrained.fptrunc.f16.f32(float -2.000000e+00, metadata !"round.tonearest", metadata !"fpexcept.strict")

‎clang/test/CodeGen/regcall.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ void __regcall hfa3(double a, double b, double c, double d, double e, struct HFA
6060
// Because they are not classified as homogeneous, they don't get special
6161
// handling to ensure alignment.
6262
void __regcall hfa4(struct HFA5 a) {}
63-
// X32: define dso_local x86_regcallcc void @__regcall3__hfa4(ptr noundef byval(%struct.HFA5) align 4 %{{.*}})
63+
// X86: define dso_local x86_regcallcc void @__regcall3__hfa4(ptr noundef byval(%struct.HFA5) align 4 %{{.*}})
6464
// Win64: define dso_local x86_regcallcc void @__regcall3__hfa4(ptr noundef %a)
6565
// Lin64: define dso_local x86_regcallcc void @__regcall3__hfa4(double %a.coerce0, double %a.coerce1, double %a.coerce2, double %a.coerce3, double %a.coerce4)
6666

‎clang/test/CodeGen/regcall4.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ void __regcall hfa3(double a, double b, double c, double d, double e, struct HFA
6060
// Because they are not classified as homogeneous, they don't get special
6161
// handling to ensure alignment.
6262
void __regcall hfa4(struct HFA5 a) {}
63-
// X32: define dso_local x86_regcallcc void @__regcall4__hfa4(ptr noundef byval(%struct.HFA5) align 4 %{{.*}})
63+
// X86: define dso_local x86_regcallcc void @__regcall4__hfa4(ptr noundef byval(%struct.HFA5) align 4 %{{.*}})
6464
// Win64: define dso_local x86_regcallcc void @__regcall4__hfa4(ptr noundef %a)
6565
// Lin64: define dso_local x86_regcallcc void @__regcall4__hfa4(double %a.coerce0, double %a.coerce1, double %a.coerce2, double %a.coerce3, double %a.coerce4)
6666

‎clang/test/CodeGen/tbaa-class.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -272,10 +272,10 @@ uint32_t g14(StructM2 *M, StructS *S) {
272272
// OLD-PATH: [[TYPE_D]] = !{!"_ZTS7StructD", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28, [[TYPE_CHAR]], i64 32}
273273
// OLD-PATH: [[TAG_M1_f16_2]] = !{[[TYPE_M1:!.*]], [[TYPE_SHORT]], i64 12}
274274
// OLD-PATH: [[TYPE_M1]] = !{!"_ZTS8StructM1", [[TYPE_S]], i64 0, [[TYPE_T:!.*]], i64 8, [[TYPE_SHORT]], i64 12}
275-
// OLD_PATH: [[TYPE_T]] = !{!"_ZTS7StructT", [[TYPE_INT]], i64 0}
275+
// OLD-PATH: [[TYPE_T]] = !{!"_ZTS7StructT", [[TYPE_INT]], i64 0}
276276
// OLD-PATH: [[TAG_M2_f16_2]] = !{[[TYPE_M2:!.*]], [[TYPE_SHORT]], i64 20}
277277
// OLD-PATH: [[TYPE_M2]] = !{!"_ZTS8StructM2", [[TYPE_DYN:!.*]], i64 0, [[TYPE_S]], i64 12, [[TYPE_SHORT]], i64 20}
278-
// OLD_PATH: [[TYPE_DYN]] = !{!"_ZTS9StructDyn", [[TYPE_INT]], i64 8}
278+
// OLD-PATH: [[TYPE_DYN]] = !{!"_ZTS9StructDyn", [[TYPE_INT]], i64 8}
279279

280280
// NEW-PATH: [[TYPE_CHAR:!.*]] = !{!{{.*}}, i64 1, !"omnipotent char"}
281281
// NEW-PATH: [[TAG_i32]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0, i64 4}
@@ -300,7 +300,7 @@ uint32_t g14(StructM2 *M, StructS *S) {
300300
// NEW-PATH: [[TYPE_D]] = !{[[TYPE_CHAR]], i64 36, !"_ZTS7StructD", [[TYPE_SHORT]], i64 0, i64 2, [[TYPE_B]], i64 4, i64 24, [[TYPE_INT]], i64 28, i64 4, [[TYPE_CHAR]], i64 32, i64 1}
301301
// NEW-PATH: [[TAG_M1_f16_2]] = !{[[TYPE_M1:!.*]], [[TYPE_SHORT]], i64 12, i64 2}
302302
// NEW-PATH: [[TYPE_M1]] = !{[[TYPE_CHAR]], i64 16, !"_ZTS8StructM1", [[TYPE_S]], i64 0, i64 8, [[TYPE_T:!.*]], i64 8, i64 4, [[TYPE_SHORT]], i64 12, i64 2}
303-
// NEW_PATH: [[TYPE_T]] = !{[[TYPE_CHAR]], i64 4, !"_ZTS7StructT", [[TYPE_INT]], i64 0, i64 4}
303+
// NEW-PATH: [[TYPE_T]] = !{[[TYPE_CHAR]], i64 4, !"_ZTS7StructT", [[TYPE_INT]], i64 0, i64 4}
304304
// NEW-PATH: [[TAG_M2_f16_2]] = !{[[TYPE_M2:!.*]], [[TYPE_SHORT]], i64 20, i64 2}
305305
// NEW-PATH: [[TYPE_M2]] = !{[[TYPE_CHAR]], i64 24, !"_ZTS8StructM2", [[TYPE_DYN:!.*]], i64 0, i64 12, [[TYPE_S]], i64 12, i64 8, [[TYPE_SHORT]], i64 20, i64 2}
306-
// NEW_PATH: [[TYPE_DYN]] = !{[[TYPE_CHAR]], i64 12, !"_ZTS9StructDyn", [[TYPE_INT]], i64 8, i64 4}
306+
// NEW-PATH: [[TYPE_DYN]] = !{[[TYPE_CHAR]], i64 16, !"_ZTS9StructDyn", [[TYPE_INT]], i64 8, i64 4}

‎clang/test/CodeGenCUDA/implicit-host-device-fun.cu

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,8 @@ T template_in_middle_by_host(T x) {
7272

7373
// Implicit host device template indirectly used by device function only.
7474
// Emitted on device.
75-
// DEVICE-LABEL: define {{.*}}@_Z34template_indirectly_used_by_deviceIiET_S0_(
76-
// DEVICE: ret i32 21
75+
// DEV-LABEL: define {{.*}}@_Z34template_indirectly_used_by_deviceIiET_S0_(
76+
// DEV: ret i32 21
7777
template<typename T>
7878
T template_indirectly_used_by_device(T x) {
7979
return 21;
@@ -87,8 +87,8 @@ T template_in_middle_by_device(T x) {
8787

8888
// Implicit host device template indirectly used by host device function only.
8989
// Emitted on host and device.
90-
// COMMON-LABEL: define {{.*}}@_Z39template_indirectly_used_by_host_deviceIiET_S0_(
91-
// COMMON: ret i32 31
90+
// COMM-LABEL: define {{.*}}@_Z39template_indirectly_used_by_host_deviceIiET_S0_(
91+
// COMM: ret i32 31
9292
template<typename T>
9393
T template_indirectly_used_by_host_device(T x) {
9494
return 31;

‎clang/test/CodeGenCXX/attr-mustprogress.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -395,8 +395,8 @@ void compound2() {
395395
}
396396

397397
// CXX98-NOT: mustprogress
398-
// CXX11 : mustprogress
399-
// FINITE : mustprogress
398+
// CXX11: mustprogress
399+
// FINITE: mustprogress
400400
// CHECK-LABEL: @_Z5Falsev(
401401
// CHECK-NEXT: entry:
402402
// CHECK-NEXT: br label %do.body

‎clang/test/CodeGenCXX/cxx0x-initializer-stdinitializerlist.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -238,8 +238,8 @@ void fn9() {
238238
void fn10(int i) {
239239
// CHECK-LABEL: define{{.*}} void @_Z4fn10i
240240
// CHECK: alloca [3 x i32]
241-
// CHECK-X86: call noalias nonnull align 16 ptr @_Znw{{[jm]}}
242-
// CHECK-AMDGPU: call noalias nonnull align 8 ptr @_Znw{{[jm]}}
241+
// X86: call noalias nonnull align 16 ptr @_Znw{{[jm]}}
242+
// AMDGCN: call noalias nonnull align 8 ptr @_Znw{{[jm]}}
243243
// CHECK: store i32 %
244244
// CHECK: store i32 2
245245
// CHECK: store i32 3

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