[LoongArch] Support llvm.is.fpclass for f32 and f64

is_fpclass (fj, mask)
->
sltu (r0, and (movfr2gr.[sd] (fclass.[sd] fj), (to_fclass_mask mask)))

[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_fclass_sd

Reviewed By: wangleiat

Differential Revision: https://reviews.llvm.org/D159183

Author: SixWeining

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

@@ -153,10 +153,11 @@ def : PatFprFpr<fminnum_ieee, FMIN_S, FPR32>;
 def : PatFpr<fneg, FNEG_S, FPR32>;
 def : PatFpr<fabs, FABS_S, FPR32>;
 def : PatFpr<fsqrt, FSQRT_S, FPR32>;
-
 def : Pat<(fdiv fpimm1, (fsqrt FPR32:$fj)), (FRSQRT_S FPR32:$fj)>;
-
 def : Pat<(fcanonicalize FPR32:$fj), (FMAX_S $fj, $fj)>;
+def : Pat<(is_fpclass FPR32:$fj, (i32 timm:$mask)),
+          (SLTU R0, (AND (MOVFR2GR_S (FCLASS_S FPR32:$fj)),
+                         (to_fclass_mask timm:$mask)))>;
 
 /// Setcc
 

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

@@ -142,15 +142,22 @@ def : PatFprFpr<fminnum_ieee, FMIN_D, FPR64>;
 def : PatFpr<fneg, FNEG_D, FPR64>;
 def : PatFpr<fabs, FABS_D, FPR64>;
 def : PatFpr<fsqrt, FSQRT_D, FPR64>;
-
 def : Pat<(fdiv fpimm1, (fsqrt FPR64:$fj)), (FRSQRT_D FPR64:$fj)>;
-
 def : Pat<(fcopysign FPR64:$fj, FPR32:$fk),
           (FCOPYSIGN_D FPR64:$fj, (FCVT_D_S FPR32:$fk))>;
 def : Pat<(fcopysign FPR32:$fj, FPR64:$fk),
           (FCOPYSIGN_S FPR32:$fj, (FCVT_S_D FPR64:$fk))>;
-
 def : Pat<(fcanonicalize FPR64:$fj), (FMAX_D $fj, $fj)>;
+let Predicates = [IsLA32] in {
+def : Pat<(is_fpclass FPR64:$fj, (i32 timm:$mask)),
+          (SLTU R0, (AND (MOVFR2GR_S_64 (FCLASS_D FPR64:$fj)),
+                         (to_fclass_mask timm:$mask)))>;
+} // Predicates = [IsLA32]
+let Predicates = [IsLA64] in {
+def : Pat<(is_fpclass FPR64:$fj, (i32 timm:$mask)),
+          (SLTU R0, (AND (MOVFR2GR_D (FCLASS_D FPR64:$fj)),
+                         (to_fclass_mask timm:$mask)))>;
+} // Predicates = [IsLA64]
 
 /// Setcc
 

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

@@ -170,6 +170,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
+    setOperationAction(ISD::IS_FPCLASS, MVT::f32, Legal);
     setOperationAction(ISD::FSIN, MVT::f32, Expand);
     setOperationAction(ISD::FCOS, MVT::f32, Expand);
     setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
@@ -202,6 +203,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FMA, MVT::f64, Legal);
     setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
     setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
+    setOperationAction(ISD::IS_FPCLASS, MVT::f64, Legal);
     setOperationAction(ISD::FSIN, MVT::f64, Expand);
     setOperationAction(ISD::FCOS, MVT::f64, Expand);
     setOperationAction(ISD::FSINCOS, MVT::f64, Expand);

llvm/lib/Target/LoongArch/LoongArchInstrInfo.h

@@ -88,5 +88,20 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
   const LoongArchSubtarget &STI;
 };
 
+namespace LoongArch {
+
+// Mask assignments for floating-point.
+static constexpr unsigned FClassMaskSignalingNaN = 0x001;
+static constexpr unsigned FClassMaskQuietNaN = 0x002;
+static constexpr unsigned FClassMaskNegativeInfinity = 0x004;
+static constexpr unsigned FClassMaskNegativeNormal = 0x008;
+static constexpr unsigned FClassMaskNegativeSubnormal = 0x010;
+static constexpr unsigned FClassMaskNegativeZero = 0x020;
+static constexpr unsigned FClassMaskPositiveInfinity = 0x040;
+static constexpr unsigned FClassMaskPositiveNormal = 0x080;
+static constexpr unsigned FClassMaskPositiveSubnormal = 0x100;
+static constexpr unsigned FClassMaskPositiveZero = 0x200;
+} // namespace LoongArch
+
 } // end namespace llvm
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

@@ -143,6 +143,32 @@ def loongarch_iocsrwr_d : SDNode<"LoongArchISD::IOCSRWR_D",
 def loongarch_cpucfg : SDNode<"LoongArchISD::CPUCFG", SDTUnaryOp,
                                [SDNPHasChain]>;
 
+def to_fclass_mask: SDNodeXForm<timm, [{
+  uint64_t Check = N->getZExtValue();
+  unsigned Mask = 0;
+  if (Check & fcSNan)
+    Mask |= LoongArch::FClassMaskSignalingNaN;
+  if (Check & fcQNan)
+    Mask |= LoongArch::FClassMaskQuietNaN;
+  if (Check & fcPosInf)
+    Mask |= LoongArch::FClassMaskPositiveInfinity;
+  if (Check & fcNegInf)
+    Mask |= LoongArch::FClassMaskNegativeInfinity;
+  if (Check & fcPosNormal)
+    Mask |= LoongArch::FClassMaskPositiveNormal;
+  if (Check & fcNegNormal)
+    Mask |= LoongArch::FClassMaskNegativeNormal;
+  if (Check & fcPosSubnormal)
+    Mask |= LoongArch::FClassMaskPositiveSubnormal;
+  if (Check & fcNegSubnormal)
+    Mask |= LoongArch::FClassMaskNegativeSubnormal;
+  if (Check & fcPosZero)
+    Mask |= LoongArch::FClassMaskPositiveZero;
+  if (Check & fcNegZero)
+    Mask |= LoongArch::FClassMaskNegativeZero;
+  return CurDAG->getTargetConstant(Mask, SDLoc(N), Subtarget->getGRLenVT());
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//