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[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4
This builtin maps to V_CVT_OFF_F32_I4 which treats its input as a 4-bit signed integer and returns 0.0625f * src . SWDEV-518861
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‎clang/include/clang/Basic/BuiltinsAMDGPU.def

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@@ -140,6 +140,7 @@ BUILTIN(__builtin_amdgcn_cvt_pknorm_u16, "E2Usff", "nc")
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BUILTIN(__builtin_amdgcn_cvt_pk_i16, "E2sii", "nc")
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BUILTIN(__builtin_amdgcn_cvt_pk_u16, "E2UsUiUi", "nc")
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BUILTIN(__builtin_amdgcn_cvt_pk_u8_f32, "UifUiUi", "nc")
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BUILTIN(__builtin_amdgcn_cvt_off_f32_i4, "fUi", "nc")
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BUILTIN(__builtin_amdgcn_sad_u8, "UiUiUiUi", "nc")
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BUILTIN(__builtin_amdgcn_msad_u8, "UiUiUiUi", "nc")
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BUILTIN(__builtin_amdgcn_sad_hi_u8, "UiUiUiUi", "nc")

‎clang/test/CodeGenOpenCL/builtins-amdgcn-cvt-off-f32-i4.cl

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL1.2 \
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// RUN: -emit-llvm -o - | FileCheck %s
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// CHECK-LABEL: @test_builtin_amdgcn_cvt_off_f32_i4(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: store i32 [[N:%.*]], ptr addrspace(5) [[N_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.cvt.off.f32.i4(i32 [[TMP0]])
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// CHECK-NEXT: ret float [[TMP1]]
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//
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float test_builtin_amdgcn_cvt_off_f32_i4(unsigned n) {
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return __builtin_amdgcn_cvt_off_f32_i4(n);
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}

‎clang/test/SemaOpenCL/builtins-amdgcn-cvt-off-f32-i4-err.cl

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// RUN: %clang_cc1 -triple amdgcn-- -verify -S -o - %s
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void test_builtin_amdgcn_cvt_off_f32_i4(unsigned n) {
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struct A{ unsigned x; } a;
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__builtin_amdgcn_cvt_off_f32_i4(n, n); // expected-error {{too many arguments to function call, expected 1, have 2}}
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__builtin_amdgcn_cvt_off_f32_i4(); // expected-error {{too few arguments to function call, expected 1, have 0}}
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__builtin_amdgcn_cvt_off_f32_i4(a); // expected-error {{passing '__private struct A' to parameter of incompatible type 'unsigned int'}}
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}

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

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@@ -3375,6 +3375,12 @@ def int_amdgcn_cvt_sr_fp8_f32 : ClangBuiltin<"__builtin_amdgcn_cvt_sr_fp8_f32">,
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[llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<3>>]>;
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// llvm.amdgcn.cvt.off.fp32.i4 int srcA
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def int_amdgcn_cvt_off_f32_i4: ClangBuiltin<"__builtin_amdgcn_cvt_off_f32_i4">,
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DefaultAttrsIntrinsic<[llvm_float_ty],
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[llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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//===----------------------------------------------------------------------===//
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// gfx950 intrinsics
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

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@@ -6042,6 +6042,7 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
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// TODO: Handle more intrinsics
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switch (IntrinsicID) {
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case Intrinsic::amdgcn_cubeid:
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case Intrinsic::amdgcn_cvt_off_f32_i4:
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return true;
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case Intrinsic::amdgcn_frexp_mant: {

‎llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

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@@ -729,6 +729,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
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break;
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}
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case Intrinsic::amdgcn_cvt_off_f32_i4: {
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ConstantInt *CArg = dyn_cast<ConstantInt>(II.getArgOperand(0));
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if (!CArg)
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break;
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int CI4BitAsInt = CArg->getValue().trunc(4).getSExtValue();
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float ResVal = 0.0625 * CI4BitAsInt;
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Constant *Res = ConstantFP::get(II.getType(), ResVal);
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return IC.replaceInstUsesWith(II, Res);
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}
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case Intrinsic::amdgcn_ubfe:
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case Intrinsic::amdgcn_sbfe: {
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// Decompose simple cases into standard shifts.

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

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@@ -4585,6 +4585,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_dot4_f32_bf8_bf8:
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case Intrinsic::amdgcn_cvt_f32_fp8:
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case Intrinsic::amdgcn_cvt_f32_bf8:
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case Intrinsic::amdgcn_cvt_off_f32_i4:
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case Intrinsic::amdgcn_cvt_pk_f32_fp8:
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case Intrinsic::amdgcn_cvt_pk_f32_bf8:
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case Intrinsic::amdgcn_cvt_pk_fp8_f32:

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

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@@ -1578,6 +1578,11 @@ class MovDPP8Pattern<Predicate Pred, Instruction Inst, ValueType vt> : GCNPat <
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let OtherPredicates = [Pred];
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}
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def : GCNPat <
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(f32 (int_amdgcn_cvt_off_f32_i4 i32:$src)),
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(V_CVT_OFF_F32_I4_e32 VGPR_32:$src)
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>;
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foreach vt = Reg32Types.types in {
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def : MovDPP8Pattern<isGFX10Only, V_MOV_B32_dpp8_gfx10, vt>;
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def : MovDPP8Pattern<isGFX11Only, V_MOV_B32_dpp8_gfx11, vt>;

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs %s -o - | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs %s --global-isel -o - | FileCheck %s
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declare float @llvm.amdgcn.cvt.off.f32.i4(i32)
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define amdgpu_cs float @cvt_var(i32 %a) {
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; CHECK-LABEL: cvt_var:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cvt_off_f32_i4_e32 v0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 %a)
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ret float %ret
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}
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define amdgpu_cs float @cvt_imm() {
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; CHECK-LABEL: cvt_imm:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cvt_off_f32_i4_e32 v0, 4
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; CHECK-NEXT: ; return to shader part epilog
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 4)
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ret float %ret
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}

‎llvm/test/CodeGen/AMDGPU/simplify-amdgcn.cvt.off.f32.i4.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck %s
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declare float @llvm.amdgcn.cvt.off.f32.i4(i32)
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define float @cvt_var(i32 %a) {
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; CHECK-LABEL: define float @cvt_var(
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; CHECK-SAME: i32 [[A:%.*]]) {
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; CHECK-NEXT: [[RET:%.*]] = call float @llvm.amdgcn.cvt.off.f32.i4(i32 [[A]])
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; CHECK-NEXT: ret float [[RET]]
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 %a)
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ret float %ret
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}
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define float @cvt_imm_0() {
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; CHECK-LABEL: define float @cvt_imm_0() {
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; CHECK-NEXT: ret float 0.000000e+00
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 0)
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ret float %ret
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}
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define float @cvt_imm_1() {
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; CHECK-LABEL: define float @cvt_imm_1() {
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; CHECK-NEXT: ret float 6.250000e-02
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 1)
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ret float %ret
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}
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define float @cvt_imm_2() {
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; CHECK-LABEL: define float @cvt_imm_2() {
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; CHECK-NEXT: ret float 1.250000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 2)
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ret float %ret
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}
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define float @cvt_imm_3() {
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; CHECK-LABEL: define float @cvt_imm_3() {
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; CHECK-NEXT: ret float 1.875000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 3)
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ret float %ret
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}
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define float @cvt_imm_4() {
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; CHECK-LABEL: define float @cvt_imm_4() {
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; CHECK-NEXT: ret float 2.500000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 4)
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ret float %ret
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}
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define float @cvt_imm_5() {
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; CHECK-LABEL: define float @cvt_imm_5() {
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; CHECK-NEXT: ret float 3.125000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 5)
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ret float %ret
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}
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define float @cvt_imm_6() {
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; CHECK-LABEL: define float @cvt_imm_6() {
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; CHECK-NEXT: ret float 3.750000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 6)
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ret float %ret
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}
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define float @cvt_imm_7() {
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; CHECK-LABEL: define float @cvt_imm_7() {
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; CHECK-NEXT: ret float 4.375000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 7)
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ret float %ret
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}
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define float @cvt_imm_8() {
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; CHECK-LABEL: define float @cvt_imm_8() {
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; CHECK-NEXT: ret float -5.000000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 8)
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ret float %ret
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}
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define float @cvt_imm_9() {
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; CHECK-LABEL: define float @cvt_imm_9() {
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; CHECK-NEXT: ret float -4.375000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 9)
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ret float %ret
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}
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define float @cvt_imm_10() {
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; CHECK-LABEL: define float @cvt_imm_10() {
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; CHECK-NEXT: ret float -3.750000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 10)
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ret float %ret
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}
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define float @cvt_imm_11() {
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; CHECK-LABEL: define float @cvt_imm_11() {
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; CHECK-NEXT: ret float -3.125000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 11)
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ret float %ret
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}
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define float @cvt_imm_12() {
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; CHECK-LABEL: define float @cvt_imm_12() {
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; CHECK-NEXT: ret float -2.500000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 12)
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ret float %ret
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}
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define float @cvt_imm_13() {
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; CHECK-LABEL: define float @cvt_imm_13() {
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; CHECK-NEXT: ret float -1.875000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 13)
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ret float %ret
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}
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define float @cvt_imm_14() {
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; CHECK-LABEL: define float @cvt_imm_14() {
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; CHECK-NEXT: ret float -1.250000e-01
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 14)
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ret float %ret
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}
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define float @cvt_imm_15() {
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; CHECK-LABEL: define float @cvt_imm_15() {
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; CHECK-NEXT: ret float -6.250000e-02
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 15)
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ret float %ret
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}
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define float @cvt_imm_underflow() {
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; CHECK-LABEL: define float @cvt_imm_underflow() {
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; CHECK-NEXT: ret float -6.250000e-02
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 -1)
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ret float %ret
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}
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define float @cvt_imm_overflow() {
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; CHECK-LABEL: define float @cvt_imm_overflow() {
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; CHECK-NEXT: ret float 0.000000e+00
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;
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%ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 16)
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ret float %ret
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}

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