[X86][CodeGen] Fix compile crash in EVEX compression for corner case

The base register of OPmi_ND may be allocated to the same physic
register as the ND operand.

OPmi_ND is not compressible b/c it has different semnatic from OPmi.
In this case, `isRedundantNewDataDest` should return false, otherwise
we would get error

Assertion `!IsNDLike && "Missing entry for ND-like instruction"' failed.

Author: KanRobert

llvm/lib/Target/X86/X86CompressEVEX.cpp

@@ -189,7 +189,7 @@ static bool isRedundantNewDataDest(MachineInstr &MI, const X86Subtarget &ST) {
   const MCInstrDesc &Desc = MI.getDesc();
   Register Reg0 = MI.getOperand(0).getReg();
   const MachineOperand &Op1 = MI.getOperand(1);
-  if (!Op1.isReg())
+  if (!Op1.isReg() || X86::getFirstAddrOperandIdx(MI) == 1)
     return false;
   Register Reg1 = Op1.getReg();
   if (Reg1 == Reg0)

llvm/test/CodeGen/X86/apx/compress-evex.mir

@@ -52,6 +52,15 @@ body:             |
     RET64 $rax
 ...
 ---
+name:            ndd_2_non_ndd_mem
+body:             |
+  bb.0.entry:
+    ; CHECK: addq    $123456, (%rax), %rax           # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x00,0x40,0xe2,0x01,0x00]
+    renamable $rax = MOV64rm $noreg, 1, $noreg, 0, $fs
+    renamable $rax = nsw ADD64mi32_ND killed renamable $rax, 1, $noreg, 0, $noreg, 123456, implicit-def dead $eflags
+    RET64 $rax
+...
+---
 name:            ndd_2_non_ndd_egpr
 body:             |
   bb.0.entry: