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[PowerPC] Add DFP format instructions definitions and MC tests
Add td definitions and asm/disasm tests for the dfp format instructions in ISA 3.1 section 5.6.6 Reviewed By: stefanp, kamaub Differential Revision: https://reviews.llvm.org/D154465
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‎llvm/lib/Target/PowerPC/PPCInstrDFP.td

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,5 +114,42 @@ let RA = 1 in
114114
"dctfixqq $RST, $RB", IIC_FPGeneral, []>;
115115
} // HasP10Vector
116116

117+
// 5.6.6 DFP Format Instructions
118+
defm DENBCD: XForm_S1_FRTB5r<59, 834, (outs f8rc:$FRT),
119+
(ins u1imm:$S, f8rc:$FRB),
120+
"denbcd", "$S, $FRT, $FRB", []>;
121+
defm DENBCDQ: XForm_S1_FRTB5r<63, 834, (outs fpairrc:$FRT),
122+
(ins u1imm:$S, fpairrc:$FRB),
123+
"denbcdq", "$S, $FRT, $FRB", []>;
117124
} // mayRaiseFPException
125+
126+
// 5.6.6 DFP none exception raising format instructions.
127+
defm DDEDPD: XForm_SP2_FRTB5r<59, 322, (outs f8rc:$FRT),
128+
(ins u2imm:$SP, f8rc:$FRB),
129+
"ddedpd", "$SP, $FRT, $FRB", []>;
130+
defm DDEDPDQ: XForm_SP2_FRTB5r<63, 322, (outs fpairrc:$FRT),
131+
(ins u2imm:$SP, fpairrc:$FRB),
132+
"ddedpdq", "$SP, $FRT, $FRB", []>;
133+
defm DXEX: XForm_26r<59, 354, (outs f8rc:$RST), (ins f8rc:$RB),
134+
"dxex", "$RST, $RB", NoItinerary, []>;
135+
defm DXEXQ: XForm_26r<63, 354, (outs f8rc:$RST), (ins fpairrc:$RB),
136+
"dxexq", "$RST, $RB", NoItinerary, []>;
137+
defm DIEX: XForm_base_r3xo_r<59, 866, (outs f8rc:$RST),
138+
(ins f8rc:$RA, f8rc:$RB),
139+
"diex", "$RST, $RA, $RB", []>;
140+
defm DIEXQ: XForm_base_r3xo_r<63, 866, (outs fpairrc:$RST),
141+
(ins f8rc:$RA, fpairrc:$RB),
142+
"diexq", "$RST, $RA, $RB", []>;
143+
defm DSCLI: Z22Form_FRTA5_SH6r<59, 66, (outs f8rc:$FRT),
144+
(ins f8rc:$FRA, u6imm:$SH),
145+
"dscli", "$FRT, $FRA, $SH", []>;
146+
defm DSCLIQ: Z22Form_FRTA5_SH6r<63, 66, (outs fpairrc:$FRT),
147+
(ins fpairrc:$FRA, u6imm:$SH),
148+
"dscliq", "$FRT, $FRA, $SH", []>;
149+
defm DSCRI: Z22Form_FRTA5_SH6r<59, 98, (outs f8rc:$FRT),
150+
(ins f8rc:$FRA, u6imm:$SH),
151+
"dscri", "$FRT, $FRA, $SH", []>;
152+
defm DSCRIQ: Z22Form_FRTA5_SH6r<63, 98, (outs fpairrc:$FRT),
153+
(ins fpairrc:$FRA, u6imm:$SH),
154+
"dscriq", "$FRT, $FRA, $SH", []>;
118155
} // hasNoSchedulingInfo

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1221,6 +1221,44 @@ class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
12211221
let Inst{31} = D{5}; // DX
12221222
}
12231223

1224+
class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
1225+
list<dag> pattern, InstrItinClass itin>
1226+
: I<opcode, OOL, IOL, asmstr, itin> {
1227+
bits<2> SP;
1228+
bits<5> FRT;
1229+
bits<5> FRB;
1230+
1231+
let Pattern = pattern;
1232+
1233+
bit RC = 0; // set by isRecordForm
1234+
1235+
let Inst{6 - 10} = FRT;
1236+
let Inst{11 - 12} = SP;
1237+
let Inst{13 - 15} = 0;
1238+
let Inst{16 - 20} = FRB;
1239+
let Inst{21 - 30} = xo;
1240+
let Inst{31} = RC;
1241+
}
1242+
1243+
class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1244+
string asmstr, list<dag> pattern, InstrItinClass itin>
1245+
: I<opcode, OOL, IOL, asmstr, itin> {
1246+
bit S;
1247+
bits<5> FRT;
1248+
bits<5> FRB;
1249+
1250+
let Pattern = pattern;
1251+
1252+
bit RC = 0; // set by isRecordForm
1253+
1254+
let Inst{6 - 10} = FRT;
1255+
let Inst{11} = S;
1256+
let Inst{12 - 15} = 0;
1257+
let Inst{16 - 20} = FRB;
1258+
let Inst{21 - 30} = xo;
1259+
let Inst{31} = RC;
1260+
}
1261+
12241262
class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
12251263
InstrItinClass itin, list<dag> pattern>
12261264
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -2132,6 +2170,25 @@ class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
21322170
let Inst{23-31} = xo;
21332171
}
21342172

2173+
class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
2174+
string asmstr, list<dag> pattern, InstrItinClass itin>
2175+
: I<opcode, OOL, IOL, asmstr, itin> {
2176+
2177+
bits<5> FRT;
2178+
bits<5> FRA;
2179+
bits<6> SH;
2180+
2181+
let Pattern = pattern;
2182+
2183+
bit RC = 0; // set by isRecordForm
2184+
2185+
let Inst{6 - 10} = FRT;
2186+
let Inst{11 - 15} = FRA;
2187+
let Inst{16 - 21} = SH;
2188+
let Inst{22 - 30} = xo;
2189+
let Inst{31} = RC;
2190+
}
2191+
21352192
class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
21362193
InstrItinClass itin, list<dag> pattern>
21372194
: I<opcode, OOL, IOL, asmstr, itin> {

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -730,6 +730,18 @@ def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
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731731
//===----------------------------------------------------------------------===//
732732
// PowerPC Multiclass Definitions.
733+
multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
734+
string asmbase, string asmstr, list<dag> pattern> {
735+
let BaseName = asmbase in {
736+
def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL,
737+
!strconcat(asmbase, !strconcat(" ", asmstr)),
738+
NoItinerary, pattern>, RecFormRel;
739+
let Defs = [CR1] in
740+
def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL,
741+
!strconcat(asmbase, !strconcat(". ", asmstr)),
742+
NoItinerary, []>, isRecordForm, RecFormRel;
743+
}
744+
}
733745

734746
multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
735747
string asmbase, string asmstr, InstrItinClass itin,
@@ -1043,6 +1055,32 @@ multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
10431055
}
10441056
}
10451057

1058+
multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1059+
string asmbase, string asmstr, list<dag> pattern> {
1060+
let BaseName = asmbase in {
1061+
def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
1062+
!strconcat(asmbase, !strconcat(" ", asmstr)),
1063+
pattern, NoItinerary>, RecFormRel;
1064+
let Defs = [CR1] in
1065+
def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
1066+
!strconcat(asmbase, !strconcat(". ", asmstr)),
1067+
[], NoItinerary>, isRecordForm, RecFormRel;
1068+
}
1069+
}
1070+
1071+
multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1072+
string asmbase, string asmstr, list<dag> pattern> {
1073+
let BaseName = asmbase in {
1074+
def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
1075+
!strconcat(asmbase, !strconcat(" ", asmstr)),
1076+
pattern, NoItinerary>, RecFormRel;
1077+
let Defs = [CR1] in
1078+
def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
1079+
!strconcat(asmbase, !strconcat(". ", asmstr)), [],
1080+
NoItinerary>, isRecordForm, RecFormRel;
1081+
}
1082+
}
1083+
10461084
multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
10471085
string asmbase, string asmstr, InstrItinClass itin,
10481086
list<dag> pattern> {
@@ -1128,6 +1166,19 @@ multiclass
11281166
}
11291167
}
11301168

1169+
multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1170+
string asmbase, string asmstr, list<dag> pattern> {
1171+
let BaseName = asmbase in {
1172+
def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
1173+
!strconcat(asmbase, !strconcat(" ", asmstr)),
1174+
pattern, NoItinerary>, RecFormRel;
1175+
let Defs = [CR1] in
1176+
def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
1177+
!strconcat(asmbase, !strconcat(". ", asmstr)),
1178+
[], NoItinerary>, isRecordForm, RecFormRel;
1179+
}
1180+
}
1181+
11311182
//===----------------------------------------------------------------------===//
11321183
// END OF MULTICLASS DEFINITIONS
11331184
//===----------------------------------------------------------------------===//

‎llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

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Original file line numberDiff line numberDiff line change
@@ -173,3 +173,75 @@
173173

174174
# CHECK: dctfixqq 8, 10
175175
0xfd 0x01 0x57 0xc4
176+
177+
# CHECK: ddedpd 0, 8, 10
178+
0xed 0x00 0x52 0x84
179+
180+
# CHECK: ddedpd. 0, 8, 10
181+
0xed 0x00 0x52 0x85
182+
183+
# CHECK: ddedpdq 1, 8, 10
184+
0xfd 0x08 0x52 0x84
185+
186+
# CHECK: ddedpdq. 1, 8, 10
187+
0xfd 0x08 0x52 0x85
188+
189+
# CHECK: denbcd 1, 12, 16
190+
0xed 0x90 0x86 0x84
191+
192+
# CHECK: denbcd. 0, 12, 16
193+
0xed 0x80 0x86 0x85
194+
195+
# CHECK: denbcdq 1, 12, 16
196+
0xfd 0x90 0x86 0x84
197+
198+
# CHECK: denbcdq. 0, 12, 16
199+
0xfd 0x80 0x86 0x85
200+
201+
# CHECK: dxex 8, 20
202+
0xed 0x00 0xa2 0xc4
203+
204+
# CHECK: dxex. 8, 20
205+
0xed 0x00 0xa2 0xc5
206+
207+
# CHECK: dxexq 8, 20
208+
0xfd 0x00 0xa2 0xc4
209+
210+
# CHECK: dxexq. 8, 20
211+
0xfd 0x00 0xa2 0xc5
212+
213+
# CHECK: diex 8, 12, 18
214+
0xed 0x0c 0x96 0xc4
215+
216+
# CHECK: diex. 8, 12, 18
217+
0xed 0x0c 0x96 0xc5
218+
219+
# CHECK: diexq. 8, 12, 18
220+
0xfd 0x0c 0x96 0xc5
221+
222+
# CHECK: diexq 8, 12, 18
223+
0xfd 0x0c 0x96 0xc4
224+
225+
# CHECK: dscli 22, 4, 63
226+
0xee 0xc4 0xfc 0x84
227+
228+
# CHECK: dscli. 22, 4, 63
229+
0xee 0xc4 0xfc 0x85
230+
231+
# CHECK: dscliq 22, 4, 63
232+
0xfe 0xc4 0xfc 0x84
233+
234+
# CHECK: dscliq. 22, 4, 63
235+
0xfe 0xc4 0xfc 0x85
236+
237+
# CHECK: dscri 16, 10, 50
238+
0xee 0x0a 0xc8 0xc4
239+
240+
# CHECK: dscri. 16, 10, 50
241+
0xee 0x0a 0xc8 0xc5
242+
243+
# CHECK: dscriq 16, 10, 50
244+
0xfe 0x0a 0xc8 0xc4
245+
246+
# CHECK: dscriq. 16, 10, 50
247+
0xfe 0x0a 0xc8 0xc5

‎llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,3 +176,75 @@
176176
# CHECK-LE: dctfixqq 8, 10 # encoding: [0xc4,0x57,0x01,0xfd]
177177
# CHECK-BE: dctfixqq 8, 10 # encoding: [0xfd,0x01,0x57,0xc4]
178178
dctfixqq 8, 10
179+
# CHECK-BE: ddedpd 0, 8, 10 # encoding: [0xed,0x00,0x52,0x84]
180+
# CHECK-LE: ddedpd 0, 8, 10 # encoding: [0x84,0x52,0x00,0xed]
181+
ddedpd 0, 8, 10
182+
# CHECK-BE: ddedpd. 0, 8, 10 # encoding: [0xed,0x00,0x52,0x85]
183+
# CHECK-LE: ddedpd. 0, 8, 10 # encoding: [0x85,0x52,0x00,0xed]
184+
ddedpd. 0, 8, 10
185+
# CHECK-BE: ddedpdq 1, 8, 10 # encoding: [0xfd,0x08,0x52,0x84]
186+
# CHECK-LE: ddedpdq 1, 8, 10 # encoding: [0x84,0x52,0x08,0xfd]
187+
ddedpdq 1, 8, 10
188+
# CHECK-BE: ddedpdq. 1, 8, 10 # encoding: [0xfd,0x08,0x52,0x85]
189+
# CHECK-LE: ddedpdq. 1, 8, 10 # encoding: [0x85,0x52,0x08,0xfd]
190+
ddedpdq. 1, 8, 10
191+
# CHECK-BE: denbcd 1, 12, 16 # encoding: [0xed,0x90,0x86,0x84]
192+
# CHECK-LE: denbcd 1, 12, 16 # encoding: [0x84,0x86,0x90,0xed]
193+
denbcd 1, 12, 16
194+
# CHECK-BE: denbcd. 0, 12, 16 # encoding: [0xed,0x80,0x86,0x85]
195+
# CHECK-LE: denbcd. 0, 12, 16 # encoding: [0x85,0x86,0x80,0xed]
196+
denbcd. 0, 12, 16
197+
# CHECK-BE: denbcdq 1, 12, 16 # encoding: [0xfd,0x90,0x86,0x84]
198+
# CHECK-LE: denbcdq 1, 12, 16 # encoding: [0x84,0x86,0x90,0xfd]
199+
denbcdq 1, 12, 16
200+
# CHECK-BE: denbcdq. 0, 12, 16 # encoding: [0xfd,0x80,0x86,0x85]
201+
# CHECK-LE: denbcdq. 0, 12, 16 # encoding: [0x85,0x86,0x80,0xfd]
202+
denbcdq. 0, 12, 16
203+
# CHECK-BE: dxex 8, 20 # encoding: [0xed,0x00,0xa2,0xc4]
204+
# CHECK-LE: dxex 8, 20 # encoding: [0xc4,0xa2,0x00,0xed]
205+
dxex 8, 20
206+
# CHECK-BE: dxex. 8, 20 # encoding: [0xed,0x00,0xa2,0xc5]
207+
# CHECK-LE: dxex. 8, 20 # encoding: [0xc5,0xa2,0x00,0xed]
208+
dxex. 8, 20
209+
# CHECK-BE: dxexq 8, 20 # encoding: [0xfd,0x00,0xa2,0xc4]
210+
# CHECK-LE: dxexq 8, 20 # encoding: [0xc4,0xa2,0x00,0xfd]
211+
dxexq 8, 20
212+
# CHECK-BE: dxexq. 8, 20 # encoding: [0xfd,0x00,0xa2,0xc5]
213+
# CHECK-LE: dxexq. 8, 20 # encoding: [0xc5,0xa2,0x00,0xfd]
214+
dxexq. 8, 20
215+
# CHECK-BE: diex 8, 12, 18 # encoding: [0xed,0x0c,0x96,0xc4]
216+
# CHECK-LE: diex 8, 12, 18 # encoding: [0xc4,0x96,0x0c,0xed]
217+
diex 8, 12, 18
218+
# CHECK-BE: diex. 8, 12, 18 # encoding: [0xed,0x0c,0x96,0xc5]
219+
# CHECK-LE: diex. 8, 12, 18 # encoding: [0xc5,0x96,0x0c,0xed]
220+
diex. 8, 12, 18
221+
# CHECK-BE: diexq 8, 12, 18 # encoding: [0xfd,0x0c,0x96,0xc4]
222+
# CHECK-LE: diexq 8, 12, 18 # encoding: [0xc4,0x96,0x0c,0xfd]
223+
diexq 8, 12, 18
224+
# CHECK-BE: diexq. 8, 12, 18 # encoding: [0xfd,0x0c,0x96,0xc5]
225+
# CHECK-LE: diexq. 8, 12, 18 # encoding: [0xc5,0x96,0x0c,0xfd]
226+
diexq. 8, 12, 18
227+
# CHECK-BE: dscli 22, 4, 63 # encoding: [0xee,0xc4,0xfc,0x84]
228+
# CHECK-LE: dscli 22, 4, 63 # encoding: [0x84,0xfc,0xc4,0xee]
229+
dscli 22, 4, 63
230+
# CHECK-BE: dscli. 22, 4, 63 # encoding: [0xee,0xc4,0xfc,0x85]
231+
# CHECK-LE: dscli. 22, 4, 63 # encoding: [0x85,0xfc,0xc4,0xee]
232+
dscli. 22, 4, 63
233+
# CHECK-BE: dscliq 22, 4, 63 # encoding: [0xfe,0xc4,0xfc,0x84]
234+
# CHECK-LE: dscliq 22, 4, 63 # encoding: [0x84,0xfc,0xc4,0xfe]
235+
dscliq 22, 4, 63
236+
# CHECK-BE: dscliq. 22, 4, 63 # encoding: [0xfe,0xc4,0xfc,0x85]
237+
# CHECK-LE: dscliq. 22, 4, 63 # encoding: [0x85,0xfc,0xc4,0xfe]
238+
dscliq. 22, 4, 63
239+
# CHECK-BE: dscri 16, 10, 50 # encoding: [0xee,0x0a,0xc8,0xc4]
240+
# CHECK-LE: dscri 16, 10, 50 # encoding: [0xc4,0xc8,0x0a,0xee]
241+
dscri 16, 10, 50
242+
# CHECK-BE: dscri. 16, 10, 50 # encoding: [0xee,0x0a,0xc8,0xc5]
243+
# CHECK-LE: dscri. 16, 10, 50 # encoding: [0xc5,0xc8,0x0a,0xee]
244+
dscri. 16, 10, 50
245+
# CHECK-BE: dscriq 16, 10, 50 # encoding: [0xfe,0x0a,0xc8,0xc4]
246+
# CHECK-LE: dscriq 16, 10, 50 # encoding: [0xc4,0xc8,0x0a,0xfe]
247+
dscriq 16, 10, 50
248+
# CHECK-BE: dscriq. 16, 10, 50 # encoding: [0xfe,0x0a,0xc8,0xc5]
249+
# CHECK-LE: dscriq. 16, 10, 50 # encoding: [0xc5,0xc8,0x0a,0xfe]
250+
dscriq. 16, 10, 50

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