[RISCV] Add MC support of RISCV Zcb Extension

This patch add the instructions of Zcb extension.

Instructions in zcb extensions shorten part of bit manipulation instructions.

Co-authored-by: Craig Topper <[email protected]>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D131141

Author: Xinlong-Wu

clang/test/Preprocessor/riscv-target-features.c

@@ -44,6 +44,8 @@
 // CHECK-NOT: __riscv_svpbmt
 // CHECK-NOT: __riscv_svinval
 // CHECK-NOT: __riscv_xventanacondops
+// CHECK-NOT: __riscv_zca
+// CHECK-NOT: __riscv_zcb
 // CHECK-NOT: __riscv_zcd
 // CHECK-NOT: __riscv_zcf
 // CHECK-NOT: __riscv_h
@@ -464,6 +466,19 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
 // CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}}
 
+// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// CHECK-ZCA-EXT: __riscv_zca 70000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// CHECK-ZCB-EXT: __riscv_zca 70000{{$}}
+// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}}
+
 // RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \

llvm/docs/RISCVUsage.rst

@@ -144,6 +144,9 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-zcf``
   LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
 
+``experimental-zcb``
+  LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+
 ``experimental-zihintntl``
   LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
 

llvm/docs/ReleaseNotes.rst

@@ -100,6 +100,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -----------------------------
 
+* Assembler support for the Zcb extension was added.
+
 Changes to the WebAssembly Backend
 ----------------------------------
 

llvm/lib/Support/RISCVISAInfo.cpp

@@ -115,6 +115,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{0, 70}},
+    {"zcb", RISCVExtensionVersion{0, 70}},
     {"zcd", RISCVExtensionVersion{0, 70}},
     {"zcf", RISCVExtensionVersion{0, 70}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
@@ -826,6 +827,7 @@ static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
+static const char *ImpliedExtsZcb[] = {"zca"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -842,6 +844,7 @@ struct ImpliedExtsEntry {
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
+    {{"zcb"}, {ImpliedExtsZcb}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -618,6 +618,16 @@ struct RISCVOperand : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm2Lsb0() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isShiftedUInt<1, 1>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm7Lsb00() const {
     if (!isImm())
       return false;
@@ -1151,6 +1161,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm2:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+  case Match_InvalidUImm2Lsb0:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
+                                      "immediate must be one of");
   case Match_InvalidUImm3:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
   case Match_InvalidUImm5:

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -43,7 +43,8 @@ enum {
   InstFormatCA = 14,
   InstFormatCB = 15,
   InstFormatCJ = 16,
-  InstFormatOther = 17,
+  InstFormatCSZN = 17,
+  InstFormatOther = 18,
 
   InstFormatMask = 31,
   InstFormatShift = 0,
@@ -234,6 +235,7 @@ namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -299,6 +299,14 @@ def HasStdExtCOrZca
                                    "'Zca' (part of the C extension, excluding "
                                    "compressed floating point loads/stores)">;
 
+def FeatureExtZcb
+    : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
+                       "'Zcb' (Compressed basic bit manipulation instructions)",
+                       [FeatureExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+                             AssemblerPredicate<(all_of FeatureExtZcb),
+                             "'Zcb' (Compressed basic bit manipulation instructions)">;
+
 def FeatureExtZcd
     : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
                        "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -47,7 +47,8 @@ def InstFormatCS     : InstFormat<13>;
 def InstFormatCA     : InstFormat<14>;
 def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
-def InstFormatOther  : InstFormat<17>;
+def InstFormatCSZN   : InstFormat<17>;
+def InstFormatOther  : InstFormat<18>;
 
 class RISCVVConstraint<bits<3> val> {
   bits<3> Value = val;

llvm/lib/Target/RISCV/RISCVInstrFormatsC.td

@@ -157,3 +157,14 @@ class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
   let Inst{2} = offset{4};
   let Inst{1-0} = opcode;
 }
+
+class RVInst16CSZN<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
+                   dag ins, string opcodestr, string argstr>
+    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSZN>{
+  bits<3> rd;
+
+  let Inst{15-10} = funct6;
+  let Inst{9-7} = rd;
+  let Inst{6-2} = funct5;
+  let Inst{1-0} = opcode;
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1620,6 +1620,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         CASE_OPERAND_UIMM(4)
         CASE_OPERAND_UIMM(5)
         CASE_OPERAND_UIMM(7)
+        CASE_OPERAND_UIMM(12)
+        CASE_OPERAND_UIMM(20)
+          // clang-format on
+        case RISCVOp::OPERAND_UIMM2_LSB0:
+          Ok = isShiftedUInt<1, 1>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM7_LSB00:
           Ok = isShiftedUInt<5, 2>(Imm);
           break;
@@ -1629,9 +1635,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         case RISCVOp::OPERAND_UIMM8_LSB000:
           Ok = isShiftedUInt<5, 3>(Imm);
           break;
-        CASE_OPERAND_UIMM(12)
-        CASE_OPERAND_UIMM(20)
-          // clang-format on
         case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
           Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
           break;

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -191,11 +191,17 @@ def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
   let OperandNamespace = "RISCVOp";
 }
 
-def uimm2 : Operand<XLenVT> {
+def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_UIMM2";
   let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isUInt<2>(Imm);
+  }];
 }
 
 def uimm3 : Operand<XLenVT> {
@@ -1853,6 +1859,7 @@ include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZc.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

@@ -0,0 +1,180 @@
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc*' instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the 'Zc*' compressed
+/// instruction extensions, version 0.70.4.
+/// This version is still experimental as the 'Zc*' extensions haven't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm2_lsb0 : Operand<XLenVT>,
+                 ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<2, "Lsb0">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<2>";
+  let OperandType = "OPERAND_UIMM2_LSB0";
+  let OperandNamespace = "RISCVOp";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedUInt<1, 1>(Imm);
+  }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
+  RVInst16CSZN<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
+               OpcodeStr, "$rd"> {
+  let Constraints = "$rd = $rd_wb";
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
+def C_ZEXT_W  : RVZcArith_r<0b11100 , "c.zext.w">,
+                Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in {
+def C_ZEXT_H  : RVZcArith_r<0b11010 , "c.zext.h">,
+                Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_B  : RVZcArith_r<0b11001 , "c.sext.b">,
+                Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_H  : RVZcArith_r<0b11011 , "c.sext.h">,
+                Sched<[WriteIALU, ReadIALU]>;
+}
+
+let Predicates = [HasStdExtZcb] in
+def C_ZEXT_B  : RVZcArith_r<0b11000 , "c.zext.b">,
+                Sched<[WriteIALU, ReadIALU]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
+def C_MUL     : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
+                Sched<[WriteIMul, ReadIMul, ReadIMul]>;
+
+let Predicates = [HasStdExtZcb] in {
+def C_NOT : RVZcArith_r<0b11101 , "c.not">,
+            Sched<[WriteIALU, ReadIALU]>;
+
+def C_LBU : CLoad_ri<0b100, "c.lbu", GPRC, uimm2>,
+            Sched<[WriteLDB, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b000;
+  let Inst{6-5} = imm{0,1};
+}
+
+def C_LHU : CLoad_ri<0b100, "c.lhu", GPRC, uimm2_lsb0>,
+            Sched<[WriteLDH, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b001;
+  let Inst{6} = 0b0;
+  let Inst{5} = imm{1};
+}
+
+def C_LH  : CLoad_ri<0b100, "c.lh", GPRC, uimm2_lsb0>,
+            Sched<[WriteLDH, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b001;
+  let Inst{6} = 0b1;
+  let Inst{5} = imm{1};
+}
+
+def C_SB : CStore_rri<0b100, "c.sb", GPRC, uimm2>,
+           Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b010;
+  let Inst{6-5} = imm{0,1};
+}
+
+def C_SH : CStore_rri<0b100, "c.sh", GPRC, uimm2_lsb0>, 
+           Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+  bits<2> imm;
+
+  let Inst{12-10} = 0b011;
+  let Inst{6} = 0b1;
+  let Inst{5} = imm{1};
+}
+}
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+let isCompressOnly = true in
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+                  (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
+                  (C_SEXT_B GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(SEXT_H GPRC:$rs1, GPRC:$rs1),
+                  (C_SEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(ZEXT_H_RV32 GPRC:$rs1, GPRC:$rs1),
+                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(ZEXT_H_RV64 GPRC:$rs1, GPRC:$rs1),
+                  (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
+                  (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
+def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0),
+                  (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
+                  (C_NOT GPRC:$rs1, GPRC:$rs1)>;
+}
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
+                  (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
+                  (C_SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
+                  (C_SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+}// Predicates = [HasStdExtZcb]
+
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb] in {
+def : InstAlias<"c.lbu $rd, (${rs1})",(C_LBU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lhu $rd, (${rs1})",(C_LHU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lh $rd, (${rs1})", (C_LH GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sb $rd, (${rs1})", (C_SB GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sh $rd, (${rs1})", (C_SH GPRC:$rd, GPRC:$rs1, 0)>;
+}