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15 | 15 | #include "Inputs/cuda.h"
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16 | 16 |
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17 | 17 | //.
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18 |
| -// CUDA: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" |
| 18 | +// CUDA: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00", section ".llvm.rodata.offloading", align 1 |
19 | 19 | // CUDA: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1
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20 |
| -// CUDA: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" |
| 20 | +// CUDA: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00", section ".llvm.rodata.offloading", align 1 |
21 | 21 | // CUDA: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1
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22 |
| -// CUDA: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" |
| 22 | +// CUDA: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00", section ".llvm.rodata.offloading", align 1 |
23 | 23 | // CUDA: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries", align 1
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24 |
| -// CUDA: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" |
| 24 | +// CUDA: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00", section ".llvm.rodata.offloading", align 1 |
25 | 25 | // CUDA: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries", align 1
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26 |
| -// CUDA: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" |
| 26 | +// CUDA: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00", section ".llvm.rodata.offloading", align 1 |
27 | 27 | // CUDA: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries", align 1
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28 | 28 | //.
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29 |
| -// HIP: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" |
| 29 | +// HIP: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00", section ".llvm.rodata.offloading", align 1 |
30 | 30 | // HIP: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1
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31 |
| -// HIP: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" |
| 31 | +// HIP: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00", section ".llvm.rodata.offloading", align 1 |
32 | 32 | // HIP: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1
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33 |
| -// HIP: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" |
| 33 | +// HIP: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00", section ".llvm.rodata.offloading", align 1 |
34 | 34 | // HIP: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries", align 1
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35 |
| -// HIP: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" |
| 35 | +// HIP: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00", section ".llvm.rodata.offloading", align 1 |
36 | 36 | // HIP: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries", align 1
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37 |
| -// HIP: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" |
| 37 | +// HIP: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00", section ".llvm.rodata.offloading", align 1 |
38 | 38 | // HIP: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries", align 1
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39 | 39 | //.
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40 |
| -// CUDA-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" |
| 40 | +// CUDA-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00", section ".llvm.rodata.offloading", align 1 |
41 | 41 | // CUDA-COFF: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1
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42 |
| -// CUDA-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" |
| 42 | +// CUDA-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00", section ".llvm.rodata.offloading", align 1 |
43 | 43 | // CUDA-COFF: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1
|
44 |
| -// CUDA-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" |
| 44 | +// CUDA-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00", section ".llvm.rodata.offloading", align 1 |
45 | 45 | // CUDA-COFF: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1
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46 |
| -// CUDA-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" |
| 46 | +// CUDA-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00", section ".llvm.rodata.offloading", align 1 |
47 | 47 | // CUDA-COFF: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries$OE", align 1
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48 |
| -// CUDA-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" |
| 48 | +// CUDA-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00", section ".llvm.rodata.offloading", align 1 |
49 | 49 | // CUDA-COFF: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries$OE", align 1
|
50 | 50 | //.
|
51 |
| -// HIP-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" |
| 51 | +// HIP-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00", section ".llvm.rodata.offloading", align 1 |
52 | 52 | // HIP-COFF: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1
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53 |
| -// HIP-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" |
| 53 | +// HIP-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00", section ".llvm.rodata.offloading", align 1 |
54 | 54 | // HIP-COFF: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1
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55 |
| -// HIP-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" |
| 55 | +// HIP-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00", section ".llvm.rodata.offloading", align 1 |
56 | 56 | // HIP-COFF: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1
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57 |
| -// HIP-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" |
| 57 | +// HIP-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00", section ".llvm.rodata.offloading", align 1 |
58 | 58 | // HIP-COFF: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries$OE", align 1
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59 |
| -// HIP-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" |
| 59 | +// HIP-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00", section ".llvm.rodata.offloading", align 1 |
60 | 60 | // HIP-COFF: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries$OE", align 1
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61 | 61 | //.
|
62 | 62 | // CUDA-LABEL: @_Z18__device_stub__foov(
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@@ -137,3 +137,28 @@ template <typename T, int dim = 1, int mode = 0>
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137 | 137 | struct __attribute__((device_builtin_texture_type)) texture : public textureReference {};
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138 | 138 |
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139 | 139 | texture<void> tex;
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| 140 | +//. |
| 141 | +// CUDA: [[META0:![0-9]+]] = !{ptr @.offloading.entry_name} |
| 142 | +// CUDA: [[META1:![0-9]+]] = !{ptr @.offloading.entry_name.1} |
| 143 | +// CUDA: [[META2:![0-9]+]] = !{ptr @.offloading.entry_name.2} |
| 144 | +// CUDA: [[META3:![0-9]+]] = !{ptr @.offloading.entry_name.3} |
| 145 | +// CUDA: [[META4:![0-9]+]] = !{ptr @.offloading.entry_name.4} |
| 146 | +//. |
| 147 | +// HIP: [[META0:![0-9]+]] = !{ptr @.offloading.entry_name} |
| 148 | +// HIP: [[META1:![0-9]+]] = !{ptr @.offloading.entry_name.1} |
| 149 | +// HIP: [[META2:![0-9]+]] = !{ptr @.offloading.entry_name.2} |
| 150 | +// HIP: [[META3:![0-9]+]] = !{ptr @.offloading.entry_name.3} |
| 151 | +// HIP: [[META4:![0-9]+]] = !{ptr @.offloading.entry_name.4} |
| 152 | +//. |
| 153 | +// CUDA-COFF: [[META0:![0-9]+]] = !{ptr @.offloading.entry_name} |
| 154 | +// CUDA-COFF: [[META1:![0-9]+]] = !{ptr @.offloading.entry_name.1} |
| 155 | +// CUDA-COFF: [[META2:![0-9]+]] = !{ptr @.offloading.entry_name.2} |
| 156 | +// CUDA-COFF: [[META3:![0-9]+]] = !{ptr @.offloading.entry_name.3} |
| 157 | +// CUDA-COFF: [[META4:![0-9]+]] = !{ptr @.offloading.entry_name.4} |
| 158 | +//. |
| 159 | +// HIP-COFF: [[META0:![0-9]+]] = !{ptr @.offloading.entry_name} |
| 160 | +// HIP-COFF: [[META1:![0-9]+]] = !{ptr @.offloading.entry_name.1} |
| 161 | +// HIP-COFF: [[META2:![0-9]+]] = !{ptr @.offloading.entry_name.2} |
| 162 | +// HIP-COFF: [[META3:![0-9]+]] = !{ptr @.offloading.entry_name.3} |
| 163 | +// HIP-COFF: [[META4:![0-9]+]] = !{ptr @.offloading.entry_name.4} |
| 164 | +//. |
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