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kosarevkosarev
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[AMDGPU][NFCI] Declare offset0/1 operands to be i32. (#100560)
Being of type i8 makes them signed, which they aren't, and requires extra work masking them on verbalisation. Part of <#62629>.
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-28
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5 files changed

+20
-28
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1270,8 +1270,8 @@ bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
12701270
// (add n0, c0)
12711271
if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) {
12721272
Base = N0;
1273-
Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
1274-
Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
1273+
Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i32);
1274+
Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i32);
12751275
return true;
12761276
}
12771277
} else if (Addr.getOpcode() == ISD::SUB) {
@@ -1306,8 +1306,10 @@ bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
13061306
SubOp, DL, MVT::getIntegerVT(Size * 8), Opnds);
13071307

13081308
Base = SDValue(MachineSub, 0);
1309-
Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
1310-
Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
1309+
Offset0 =
1310+
CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i32);
1311+
Offset1 =
1312+
CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i32);
13111313
return true;
13121314
}
13131315
}
@@ -1321,17 +1323,17 @@ bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
13211323
MachineSDNode *MovZero =
13221324
CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32, Zero);
13231325
Base = SDValue(MovZero, 0);
1324-
Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
1325-
Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
1326+
Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i32);
1327+
Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i32);
13261328
return true;
13271329
}
13281330
}
13291331

13301332
// default case
13311333

13321334
Base = Addr;
1333-
Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
1334-
Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
1335+
Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i32);
1336+
Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i32);
13351337
return true;
13361338
}
13371339

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -852,24 +852,24 @@ def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
852852
}
853853

854854
class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
855-
(vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
855+
(vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i32:$offset0, i32:$offset1))),
856856
(inst $ptr, $offset0, $offset1, (i1 0))
857857
>;
858858

859859
class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
860-
(frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
860+
(frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i32:$offset0, i32:$offset1)),
861861
(inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
862862
(i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
863863
(i1 0))
864864
>;
865865

866866
class DS128Bit8ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
867-
(vt:$value (frag (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
867+
(vt:$value (frag (DS128Bit8ByteAligned i32:$ptr, i32:$offset0, i32:$offset1))),
868868
(inst $ptr, $offset0, $offset1, (i1 0))
869869
>;
870870

871871
class DS128Bit8ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
872-
(frag vt:$value, (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
872+
(frag vt:$value, (DS128Bit8ByteAligned i32:$ptr, i32:$offset0, i32:$offset1)),
873873
(inst $ptr, (i64 (EXTRACT_SUBREG VReg_128:$value, sub0_sub1)),
874874
(i64 (EXTRACT_SUBREG VReg_128:$value, sub2_sub3)), $offset0, $offset1,
875875
(i1 0))

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -76,11 +76,6 @@ void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo,
7676
O << formatDec(MI->getOperand(OpNo).getImm() & 0xf);
7777
}
7878

79-
void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
80-
raw_ostream &O) {
81-
O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
82-
}
83-
8479
void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
8580
raw_ostream &O) {
8681
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
@@ -138,19 +133,15 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
138133
void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
139134
const MCSubtargetInfo &STI,
140135
raw_ostream &O) {
141-
if (MI->getOperand(OpNo).getImm()) {
142-
O << " offset0:";
143-
printU8ImmDecOperand(MI, OpNo, O);
144-
}
136+
if (int64_t Offset = MI->getOperand(OpNo).getImm())
137+
O << " offset0:" << formatDec(Offset);
145138
}
146139

147140
void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
148141
const MCSubtargetInfo &STI,
149142
raw_ostream &O) {
150-
if (MI->getOperand(OpNo).getImm()) {
151-
O << " offset1:";
152-
printU8ImmDecOperand(MI, OpNo, O);
153-
}
143+
if (int64_t Offset = MI->getOperand(OpNo).getImm())
144+
O << " offset1:" << formatDec(Offset);
154145
}
155146

156147
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
4141
void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
4242
const MCSubtargetInfo &STI, raw_ostream &O);
4343
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44-
void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4544
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4645
void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
4746
const MCSubtargetInfo &STI, raw_ostream &O);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1067,8 +1067,8 @@ let ImmTy = "ImmTyOffset" in
10671067
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
10681068
def Offset : NamedIntOperand<i32, "offset">;
10691069
let Validator = "isUInt<8>" in {
1070-
def Offset0 : NamedIntOperand<i8, "offset0">;
1071-
def Offset1 : NamedIntOperand<i8, "offset1">;
1070+
def Offset0 : NamedIntOperand<i32, "offset0">;
1071+
def Offset1 : NamedIntOperand<i32, "offset1">;
10721072
}
10731073

10741074
def gds : NamedBitOperand<"gds", "GDS">;

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