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michaelmaitlandwangpc-pp
michaelmaitland
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[RISCV] Split widening floating point fused multiple-add pseudo instructions by SEW
Co-authored-by: Wang Pengcheng <[email protected]>
1 parent c6b7944 commit 43248ff

9 files changed

+74
-73
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2943,9 +2943,9 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
29432943
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
29442944

29452945
#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \
2946-
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, VV, MF4, E16) \
29472946
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E16) \
2948-
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32)
2947+
CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \
2948+
CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)
29492949

29502950
#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW) \
29512951
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 35 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -3287,10 +3287,10 @@ multiclass VPseudoTernaryW_VV<LMULInfo m> {
32873287
constraint, /*Commutable*/ 0, TargetConstraintType=3>;
32883288
}
32893289

3290-
multiclass VPseudoTernaryW_VV_RM<LMULInfo m> {
3290+
multiclass VPseudoTernaryW_VV_RM<LMULInfo m, int sew = 0> {
32913291
defvar constraint = "@earlyclobber $rd";
32923292
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
3293-
constraint, /* Commutable */ 0,
3293+
constraint, sew, /* Commutable */ 0,
32943294
TargetConstraintType=3>;
32953295
}
32963296

@@ -3306,11 +3306,11 @@ multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f, int TargetConstraintType =
33063306
m.vrclass, m, constraint, /*Commutable*/ 0, TargetConstraintType>;
33073307
}
33083308

3309-
multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f> {
3309+
multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
33103310
defvar constraint = "@earlyclobber $rd";
33113311
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,
33123312
m.vrclass, m, constraint,
3313-
/* Commutable */ 0,
3313+
sew, /* Commutable */ 0,
33143314
TargetConstraintType=3>;
33153315
}
33163316

@@ -3396,34 +3396,36 @@ multiclass VPseudoVWMAC_VX {
33963396

33973397
multiclass VPseudoVWMAC_VV_VF_RM {
33983398
foreach m = MxListFW in {
3399-
defm "" : VPseudoTernaryW_VV_RM<m>,
3400-
SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
3401-
"ReadVFWMulAddV", "ReadVFWMulAddV", m.MX>;
3399+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3400+
defm "" : VPseudoTernaryW_VV_RM<m, sew=e>,
3401+
SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
3402+
"ReadVFWMulAddV", "ReadVFWMulAddV", m.MX, e>;
34023403
}
34033404

34043405
foreach f = FPListW in {
34053406
foreach m = f.MxListFW in {
3406-
defm "" : VPseudoTernaryW_VF_RM<m, f>,
3407+
defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,
34073408
SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",
3408-
"ReadVFWMulAddF", "ReadVFWMulAddV", m.MX>;
3409+
"ReadVFWMulAddF", "ReadVFWMulAddV", m.MX, f.SEW>;
34093410
}
34103411
}
34113412
}
34123413

34133414
multiclass VPseudoVWMAC_VV_VF_BF_RM {
34143415
foreach m = MxListFW in {
34153416
defvar mx = m.MX;
3416-
defm "" : VPseudoTernaryW_VV_RM<m>,
3417-
SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
3418-
"ReadVFWMulAddV", "ReadVFWMulAddV", mx>;
3417+
foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in
3418+
defm "" : VPseudoTernaryW_VV_RM<m, sew=e>,
3419+
SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
3420+
"ReadVFWMulAddV", "ReadVFWMulAddV", mx, e>;
34193421
}
34203422

34213423
foreach f = BFPListW in {
34223424
foreach m = f.MxListFW in {
34233425
defvar mx = m.MX;
3424-
defm "" : VPseudoTernaryW_VF_RM<m, f>,
3426+
defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,
34253427
SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",
3426-
"ReadVFWMulAddF", "ReadVFWMulAddV", mx>;
3428+
"ReadVFWMulAddF", "ReadVFWMulAddV", mx, f.SEW>;
34273429
}
34283430
}
34293431
}
@@ -5703,7 +5705,7 @@ multiclass VPatTernaryW_VV<string intrinsic, string instruction,
57035705
}
57045706

57055707
multiclass VPatTernaryW_VV_RM<string intrinsic, string instruction,
5706-
list<VTypeInfoToWide> vtilist> {
5708+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
57075709
foreach vtiToWti = vtilist in {
57085710
defvar vti = vtiToWti.Vti;
57095711
defvar wti = vtiToWti.Wti;
@@ -5712,7 +5714,8 @@ multiclass VPatTernaryW_VV_RM<string intrinsic, string instruction,
57125714
defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV",
57135715
wti.Vector, vti.Vector, vti.Vector,
57145716
vti.Mask, vti.Log2SEW, vti.LMul,
5715-
wti.RegClass, vti.RegClass, vti.RegClass>;
5717+
wti.RegClass, vti.RegClass,
5718+
vti.RegClass, isSEWAware>;
57165719
}
57175720
}
57185721

@@ -5731,19 +5734,18 @@ multiclass VPatTernaryW_VX<string intrinsic, string instruction,
57315734
}
57325735
}
57335736

5734-
multiclass VPatTernaryW_VX_RM<string intrinsic, string instruction,
5735-
list<VTypeInfoToWide> vtilist> {
5737+
multiclass
5738+
VPatTernaryW_VX_RM<string intrinsic, string instruction,
5739+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
57365740
foreach vtiToWti = vtilist in {
57375741
defvar vti = vtiToWti.Vti;
57385742
defvar wti = vtiToWti.Wti;
57395743
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
5740-
GetVTypePredicates<wti>.Predicates) in
5741-
defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction,
5742-
"V"#vti.ScalarSuffix,
5743-
wti.Vector, vti.Scalar, vti.Vector,
5744-
vti.Mask, vti.Log2SEW, vti.LMul,
5745-
wti.RegClass, vti.ScalarRegClass,
5746-
vti.RegClass>;
5744+
GetVTypePredicates<wti>.Predicates) in defm
5745+
: VPatTernaryWithPolicyRoundingMode<
5746+
intrinsic, instruction, "V" #vti.ScalarSuffix, wti.Vector,
5747+
vti.Scalar, vti.Vector, vti.Mask, vti.Log2SEW, vti.LMul,
5748+
wti.RegClass, vti.ScalarRegClass, vti.RegClass, isSEWAware>;
57475749
}
57485750
}
57495751

@@ -5775,9 +5777,9 @@ multiclass VPatTernaryW_VV_VX<string intrinsic, string instruction,
57755777
VPatTernaryW_VX<intrinsic, instruction, vtilist>;
57765778

57775779
multiclass VPatTernaryW_VV_VX_RM<string intrinsic, string instruction,
5778-
list<VTypeInfoToWide> vtilist>
5779-
: VPatTernaryW_VV_RM<intrinsic, instruction, vtilist>,
5780-
VPatTernaryW_VX_RM<intrinsic, instruction, vtilist>;
5780+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 1>
5781+
: VPatTernaryW_VV_RM<intrinsic, instruction, vtilist, isSEWAware>,
5782+
VPatTernaryW_VX_RM<intrinsic, instruction, vtilist, isSEWAware>;
57815783

57825784
multiclass VPatBinaryM_VV_VX<string intrinsic, string instruction,
57835785
list<VTypeInfo> vtilist>
@@ -7154,16 +7156,16 @@ defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB",
71547156
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
71557157
//===----------------------------------------------------------------------===//
71567158
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmacc", "PseudoVFWMACC",
7157-
AllWidenableFloatVectors>;
7159+
AllWidenableFloatVectors, isSEWAware=1>;
71587160
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC",
7159-
AllWidenableFloatVectors>;
7161+
AllWidenableFloatVectors, isSEWAware=1>;
71607162
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC",
7161-
AllWidenableFloatVectors>;
7163+
AllWidenableFloatVectors, isSEWAware=1>;
71627164
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC",
7163-
AllWidenableFloatVectors>;
7165+
AllWidenableFloatVectors, isSEWAware=1>;
71647166
let Predicates = [HasStdExtZvfbfwma] in
71657167
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
7166-
AllWidenableBFloatToFloatVectors>;
7168+
AllWidenableBFloatToFloatVectors, isSEWAware=1>;
71677169

71687170
//===----------------------------------------------------------------------===//
71697171
// 13.8. Vector Floating-Point Square-Root Instruction

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -706,6 +706,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name> {
706706
foreach vtiToWti = AllWidenableFloatVectors in {
707707
defvar vti = vtiToWti.Vti;
708708
defvar wti = vtiToWti.Wti;
709+
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
709710
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
710711
GetVTypePredicates<wti>.Predicates) in {
711712
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
@@ -715,7 +716,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name> {
715716
(vti.Vector vti.RegClass:$rs2),
716717
(vti.Mask true_mask), (XLenVT srcvalue))),
717718
(wti.Vector wti.RegClass:$rd)),
718-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
719+
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
719720
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
720721
// Value to indicate no rounding mode change in
721722
// RISCVInsertReadWriteCSR
@@ -727,7 +728,7 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name> {
727728
(vti.Vector vti.RegClass:$rs2),
728729
(vti.Mask true_mask), (XLenVT srcvalue))),
729730
(wti.Vector wti.RegClass:$rd)),
730-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
731+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
731732
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
732733
// Value to indicate no rounding mode change in
733734
// RISCVInsertReadWriteCSR
@@ -741,6 +742,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
741742
foreach vtiToWti = AllWidenableFloatVectors in {
742743
defvar vti = vtiToWti.Vti;
743744
defvar wti = vtiToWti.Wti;
745+
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
744746
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
745747
GetVTypePredicates<wti>.Predicates) in {
746748
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
@@ -749,7 +751,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
749751
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
750752
(vti.Mask true_mask), (XLenVT srcvalue)),
751753
(fneg wti.RegClass:$rd)),
752-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
754+
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
753755
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
754756
// Value to indicate no rounding mode change in
755757
// RISCVInsertReadWriteCSR
@@ -760,7 +762,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
760762
(vti.Vector vti.RegClass:$rs2),
761763
(vti.Mask true_mask), (XLenVT srcvalue)))),
762764
(fneg wti.RegClass:$rd)),
763-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
765+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
764766
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
765767
// Value to indicate no rounding mode change in
766768
// RISCVInsertReadWriteCSR
@@ -770,7 +772,7 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF_RM<string instruction_name> {
770772
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
771773
(vti.Mask true_mask), (XLenVT srcvalue)),
772774
(fneg wti.RegClass:$rd)),
773-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
775+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
774776
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
775777
// Value to indicate no rounding mode change in
776778
// RISCVInsertReadWriteCSR
@@ -784,6 +786,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
784786
foreach vtiToWti = AllWidenableFloatVectors in {
785787
defvar vti = vtiToWti.Vti;
786788
defvar wti = vtiToWti.Wti;
789+
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
787790
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
788791
GetVTypePredicates<wti>.Predicates) in {
789792
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
@@ -792,7 +795,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
792795
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
793796
(vti.Mask true_mask), (XLenVT srcvalue)),
794797
(fneg wti.RegClass:$rd)),
795-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
798+
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
796799
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
797800
// Value to indicate no rounding mode change in
798801
// RISCVInsertReadWriteCSR
@@ -802,7 +805,7 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
802805
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
803806
(vti.Mask true_mask), (XLenVT srcvalue)),
804807
(fneg wti.RegClass:$rd)),
805-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
808+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
806809
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
807810
// Value to indicate no rounding mode change in
808811
// RISCVInsertReadWriteCSR
@@ -816,6 +819,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
816819
foreach vtiToWti = AllWidenableFloatVectors in {
817820
defvar vti = vtiToWti.Vti;
818821
defvar wti = vtiToWti.Wti;
822+
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
819823
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
820824
GetVTypePredicates<wti>.Predicates) in {
821825
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
@@ -824,7 +828,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
824828
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
825829
(vti.Mask true_mask), (XLenVT srcvalue)),
826830
wti.RegClass:$rd),
827-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
831+
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
828832
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
829833
// Value to indicate no rounding mode change in
830834
// RISCVInsertReadWriteCSR
@@ -835,7 +839,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
835839
(vti.Vector vti.RegClass:$rs2),
836840
(vti.Mask true_mask), (XLenVT srcvalue)))),
837841
wti.RegClass:$rd),
838-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
842+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
839843
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
840844
// Value to indicate no rounding mode change in
841845
// RISCVInsertReadWriteCSR
@@ -845,7 +849,7 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF_RM<string instruction_name> {
845849
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
846850
(vti.Mask true_mask), (XLenVT srcvalue)),
847851
wti.RegClass:$rd),
848-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
852+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix)
849853
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
850854
// Value to indicate no rounding mode change in
851855
// RISCVInsertReadWriteCSR

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1994,13 +1994,14 @@ multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name> {
19941994
foreach vtiToWti = AllWidenableFloatVectors in {
19951995
defvar vti = vtiToWti.Vti;
19961996
defvar wti = vtiToWti.Wti;
1997+
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
19971998
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
19981999
GetVTypePredicates<wti>.Predicates) in {
19992000
def : Pat<(vop (vti.Vector vti.RegClass:$rs1),
20002001
(vti.Vector vti.RegClass:$rs2),
20012002
(wti.Vector wti.RegClass:$rd), (vti.Mask V0),
20022003
VLOpFrag),
2003-
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX #"_MASK")
2004+
(!cast<Instruction>(instruction_name#"_VV_"#suffix#"_MASK")
20042005
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
20052006
(vti.Mask V0),
20062007
// Value to indicate no rounding mode change in
@@ -2011,7 +2012,7 @@ multiclass VPatWidenFPMulAccVL_VV_VF_RM<SDNode vop, string instruction_name> {
20112012
(vti.Vector vti.RegClass:$rs2),
20122013
(wti.Vector wti.RegClass:$rd), (vti.Mask V0),
20132014
VLOpFrag),
2014-
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX #"_MASK")
2015+
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#suffix#"_MASK")
20152016
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
20162017
(vti.Mask V0),
20172018
// Value to indicate no rounding mode change in

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