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MachineSSAUpdater: use all vreg attributes instead of reg class only (#78431)
When initializing MachineSSAUpdater save all attributes of current virtual register and create new virtual registers with same attributes. Now new virtual registers have same both register class or bank and LLT. Previously new virtual registers had same register class but LLT was not set (LLT was set to default/empty LLT). Required by GlobalISel for AMDGPU, new 'lane mask' virtual registers created by MachineSSAUpdater need to have both register class and LLT. patch 4 from: #73337
1 parent f290c00 commit 433f8e7

11 files changed

+480
-359
lines changed

‎llvm/include/llvm/CodeGen/MachineSSAUpdater.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#ifndef LLVM_CODEGEN_MACHINESSAUPDATER_H
1414
#define LLVM_CODEGEN_MACHINESSAUPDATER_H
1515

16+
#include "llvm/CodeGen/MachineRegisterInfo.h"
1617
#include "llvm/CodeGen/Register.h"
1718

1819
namespace llvm {
@@ -40,8 +41,8 @@ class MachineSSAUpdater {
4041
//typedef DenseMap<MachineBasicBlock*, Register> AvailableValsTy;
4142
void *AV = nullptr;
4243

43-
/// VRC - Register class of the current virtual register.
44-
const TargetRegisterClass *VRC = nullptr;
44+
/// Register class or bank and LLT of current virtual register.
45+
MachineRegisterInfo::VRegAttrs RegAttrs;
4546

4647
/// InsertedPHIs - If this is non-null, the MachineSSAUpdater adds all PHI
4748
/// nodes that it creates to the vector.
@@ -62,7 +63,6 @@ class MachineSSAUpdater {
6263
/// Initialize - Reset this object to get ready for a new set of SSA
6364
/// updates.
6465
void Initialize(Register V);
65-
void Initialize(const TargetRegisterClass *RC);
6666

6767
/// AddAvailableValue - Indicate that a rewritten value is available at the
6868
/// end of the specified block with the specified value.

‎llvm/lib/CodeGen/MachineSSAUpdater.cpp

Lines changed: 19 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -51,17 +51,13 @@ MachineSSAUpdater::~MachineSSAUpdater() {
5151

5252
/// Initialize - Reset this object to get ready for a new set of SSA
5353
/// updates.
54-
void MachineSSAUpdater::Initialize(const TargetRegisterClass *RC) {
54+
void MachineSSAUpdater::Initialize(Register V) {
5555
if (!AV)
5656
AV = new AvailableValsTy();
5757
else
5858
getAvailableVals(AV).clear();
5959

60-
VRC = RC;
61-
}
62-
63-
void MachineSSAUpdater::Initialize(Register V) {
64-
Initialize(MRI->getRegClass(V));
60+
RegAttrs = MRI->getVRegAttrs(V);
6561
}
6662

6763
/// HasValueForBlock - Return true if the MachineSSAUpdater already has a value for
@@ -115,13 +111,12 @@ Register LookForIdenticalPHI(MachineBasicBlock *BB,
115111
/// InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define
116112
/// a value of the given register class at the start of the specified basic
117113
/// block. It returns the virtual register defined by the instruction.
118-
static
119-
MachineInstrBuilder InsertNewDef(unsigned Opcode,
120-
MachineBasicBlock *BB, MachineBasicBlock::iterator I,
121-
const TargetRegisterClass *RC,
122-
MachineRegisterInfo *MRI,
123-
const TargetInstrInfo *TII) {
124-
Register NewVR = MRI->createVirtualRegister(RC);
114+
static MachineInstrBuilder InsertNewDef(unsigned Opcode, MachineBasicBlock *BB,
115+
MachineBasicBlock::iterator I,
116+
MachineRegisterInfo::VRegAttrs RegAttrs,
117+
MachineRegisterInfo *MRI,
118+
const TargetInstrInfo *TII) {
119+
Register NewVR = MRI->createVirtualRegister(RegAttrs);
125120
return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
126121
}
127122

@@ -158,9 +153,9 @@ Register MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB,
158153
if (ExistingValueOnly)
159154
return Register();
160155
// Insert an implicit_def to represent an undef value.
161-
MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
162-
BB, BB->getFirstTerminator(),
163-
VRC, MRI, TII);
156+
MachineInstr *NewDef =
157+
InsertNewDef(TargetOpcode::IMPLICIT_DEF, BB, BB->getFirstTerminator(),
158+
RegAttrs, MRI, TII);
164159
return NewDef->getOperand(0).getReg();
165160
}
166161

@@ -197,8 +192,8 @@ Register MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB,
197192

198193
// Otherwise, we do need a PHI: insert one now.
199194
MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin();
200-
MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB,
201-
Loc, VRC, MRI, TII);
195+
MachineInstrBuilder InsertedPHI =
196+
InsertNewDef(TargetOpcode::PHI, BB, Loc, RegAttrs, MRI, TII);
202197

203198
// Fill in all the predecessors of the PHI.
204199
for (unsigned i = 0, e = PredValues.size(); i != e; ++i)
@@ -300,10 +295,9 @@ class SSAUpdaterTraits<MachineSSAUpdater> {
300295
static Register GetUndefVal(MachineBasicBlock *BB,
301296
MachineSSAUpdater *Updater) {
302297
// Insert an implicit_def to represent an undef value.
303-
MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
304-
BB, BB->getFirstNonPHI(),
305-
Updater->VRC, Updater->MRI,
306-
Updater->TII);
298+
MachineInstr *NewDef =
299+
InsertNewDef(TargetOpcode::IMPLICIT_DEF, BB, BB->getFirstNonPHI(),
300+
Updater->RegAttrs, Updater->MRI, Updater->TII);
307301
return NewDef->getOperand(0).getReg();
308302
}
309303

@@ -312,9 +306,9 @@ class SSAUpdaterTraits<MachineSSAUpdater> {
312306
static Register CreateEmptyPHI(MachineBasicBlock *BB, unsigned NumPreds,
313307
MachineSSAUpdater *Updater) {
314308
MachineBasicBlock::iterator Loc = BB->empty() ? BB->end() : BB->begin();
315-
MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,
316-
Updater->VRC, Updater->MRI,
317-
Updater->TII);
309+
MachineInstr *PHI =
310+
InsertNewDef(TargetOpcode::PHI, BB, Loc, Updater->RegAttrs,
311+
Updater->MRI, Updater->TII);
318312
return PHI->getOperand(0).getReg();
319313
}
320314

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll

Lines changed: 53 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
22
; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
3-
; REQUIRES: do-not-run-me
43

54
; Divergent phis that don't require lowering using lane mask merging
65

@@ -66,15 +65,16 @@ exit:
6665
define amdgpu_ps void @divergent_i1_phi_uniform_branch_simple(ptr addrspace(1) %out, i32 %tid, i32 inreg %cond) {
6766
; GFX10-LABEL: divergent_i1_phi_uniform_branch_simple:
6867
; GFX10: ; %bb.0: ; %A
68+
; GFX10-NEXT: v_cmp_le_u32_e64 s1, 6, v2
6969
; GFX10-NEXT: s_cmp_lg_u32 s0, 0
70-
; GFX10-NEXT: s_cbranch_scc0 .LBB1_2
71-
; GFX10-NEXT: ; %bb.1:
72-
; GFX10-NEXT: v_cmp_le_u32_e64 s0, 6, v2
73-
; GFX10-NEXT: s_branch .LBB1_3
74-
; GFX10-NEXT: .LBB1_2: ; %B
75-
; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 1, v2
76-
; GFX10-NEXT: .LBB1_3: ; %exit
77-
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, -1, s0
70+
; GFX10-NEXT: s_cbranch_scc1 .LBB1_2
71+
; GFX10-NEXT: ; %bb.1: ; %B
72+
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 1, v2
73+
; GFX10-NEXT: s_andn2_b32 s0, s1, exec_lo
74+
; GFX10-NEXT: s_and_b32 s1, exec_lo, vcc_lo
75+
; GFX10-NEXT: s_or_b32 s1, s0, s1
76+
; GFX10-NEXT: .LBB1_2: ; %exit
77+
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, -1, s1
7878
; GFX10-NEXT: v_add_nc_u32_e32 v2, 2, v2
7979
; GFX10-NEXT: global_store_dword v[0:1], v2, off
8080
; GFX10-NEXT: s_endpgm
@@ -101,23 +101,27 @@ define void @divergent_i1_phi_used_inside_loop(float %val, ptr %addr) {
101101
; GFX10-LABEL: divergent_i1_phi_used_inside_loop:
102102
; GFX10: ; %bb.0: ; %entry
103103
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
104-
; GFX10-NEXT: s_mov_b32 s4, 0
104+
; GFX10-NEXT: s_mov_b32 s5, 0
105105
; GFX10-NEXT: v_mov_b32_e32 v3, 1
106-
; GFX10-NEXT: v_mov_b32_e32 v4, s4
106+
; GFX10-NEXT: v_mov_b32_e32 v4, s5
107+
; GFX10-NEXT: ; implicit-def: $sgpr6
107108
; GFX10-NEXT: .LBB2_1: ; %loop
108109
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
109-
; GFX10-NEXT: v_cvt_f32_u32_e32 v5, v4
110110
; GFX10-NEXT: v_xor_b32_e32 v3, 1, v3
111+
; GFX10-NEXT: v_cvt_f32_u32_e32 v5, v4
111112
; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v4
113+
; GFX10-NEXT: v_and_b32_e32 v6, 1, v3
112114
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0
113-
; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
114-
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
115+
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v6
116+
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
117+
; GFX10-NEXT: s_andn2_b32 s6, s6, exec_lo
118+
; GFX10-NEXT: s_and_b32 s4, exec_lo, s4
119+
; GFX10-NEXT: s_or_b32 s6, s6, s4
120+
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
115121
; GFX10-NEXT: s_cbranch_execnz .LBB2_1
116122
; GFX10-NEXT: ; %bb.2: ; %exit
117-
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
118-
; GFX10-NEXT: v_and_b32_e32 v0, 1, v3
119-
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
120-
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
123+
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
124+
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s6
121125
; GFX10-NEXT: flat_store_dword v[1:2], v0
122126
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
123127
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -144,44 +148,49 @@ define void @divergent_i1_phi_used_inside_loop_bigger_loop_body(float %val, floa
144148
; GFX10: ; %bb.0: ; %entry
145149
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
146150
; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, 1.0, v1
147-
; GFX10-NEXT: s_mov_b32 s4, 0
148-
; GFX10-NEXT: v_mov_b32_e32 v8, 0x3e8
149-
; GFX10-NEXT: v_mov_b32_e32 v9, s4
150-
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
151+
; GFX10-NEXT: s_mov_b32 s5, 0
152+
; GFX10-NEXT: v_mov_b32_e32 v1, 0x3e8
153+
; GFX10-NEXT: v_mov_b32_e32 v8, s5
154+
; GFX10-NEXT: ; implicit-def: $sgpr6
155+
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
151156
; GFX10-NEXT: s_branch .LBB3_2
152157
; GFX10-NEXT: .LBB3_1: ; %loop_body
153158
; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1
154-
; GFX10-NEXT: v_cvt_f32_u32_e32 v10, v9
155-
; GFX10-NEXT: v_xor_b32_e32 v1, 1, v1
156-
; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9
157-
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v0
158-
; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4
159-
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4
159+
; GFX10-NEXT: v_cvt_f32_u32_e32 v9, v8
160+
; GFX10-NEXT: s_xor_b32 s4, s4, -1
161+
; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v8
162+
; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v0
163+
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
164+
; GFX10-NEXT: s_or_b32 s5, vcc_lo, s5
165+
; GFX10-NEXT: s_andn2_b32 s6, s6, exec_lo
166+
; GFX10-NEXT: s_and_b32 s4, exec_lo, s4
167+
; GFX10-NEXT: s_or_b32 s6, s6, s4
168+
; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
160169
; GFX10-NEXT: s_cbranch_execz .LBB3_6
161170
; GFX10-NEXT: .LBB3_2: ; %loop_start
162171
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
163-
; GFX10-NEXT: v_cmp_ge_i32_e32 vcc_lo, 0x3e8, v9
164-
; GFX10-NEXT: s_mov_b32 s5, 1
172+
; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
173+
; GFX10-NEXT: v_cmp_ge_i32_e32 vcc_lo, 0x3e8, v8
174+
; GFX10-NEXT: s_mov_b32 s7, 1
175+
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v9
165176
; GFX10-NEXT: s_cbranch_vccz .LBB3_4
166177
; GFX10-NEXT: ; %bb.3: ; %else
167178
; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1
168-
; GFX10-NEXT: s_mov_b32 s5, 0
169-
; GFX10-NEXT: flat_store_dword v[6:7], v8
179+
; GFX10-NEXT: s_mov_b32 s7, 0
180+
; GFX10-NEXT: flat_store_dword v[6:7], v1
170181
; GFX10-NEXT: .LBB3_4: ; %Flow
171182
; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1
172-
; GFX10-NEXT: s_xor_b32 s5, s5, 1
173-
; GFX10-NEXT: s_and_b32 s5, s5, 1
174-
; GFX10-NEXT: s_cmp_lg_u32 s5, 0
183+
; GFX10-NEXT: s_xor_b32 s7, s7, 1
184+
; GFX10-NEXT: s_and_b32 s7, s7, 1
185+
; GFX10-NEXT: s_cmp_lg_u32 s7, 0
175186
; GFX10-NEXT: s_cbranch_scc1 .LBB3_1
176187
; GFX10-NEXT: ; %bb.5: ; %if
177188
; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1
178-
; GFX10-NEXT: flat_store_dword v[4:5], v8
189+
; GFX10-NEXT: flat_store_dword v[4:5], v1
179190
; GFX10-NEXT: s_branch .LBB3_1
180191
; GFX10-NEXT: .LBB3_6: ; %exit
181-
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
182-
; GFX10-NEXT: v_and_b32_e32 v0, 1, v1
183-
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
184-
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
192+
; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
193+
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s6
185194
; GFX10-NEXT: flat_store_dword v[2:3], v0
186195
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
187196
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -221,16 +230,15 @@ exit:
221230
define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3 x i32> inreg %.WorkgroupId, <3 x i32> %.LocalInvocationId) #0 {
222231
; GFX10-LABEL: single_lane_execution_attribute:
223232
; GFX10: ; %bb.0: ; %.entry
224-
; GFX10-NEXT: s_mov_b32 s12, 0
225233
; GFX10-NEXT: s_getpc_b64 s[4:5]
234+
; GFX10-NEXT: s_mov_b32 s12, 0
226235
; GFX10-NEXT: s_mov_b32 s13, -1
227236
; GFX10-NEXT: s_mov_b32 s2, s0
228237
; GFX10-NEXT: s_and_b64 s[4:5], s[4:5], s[12:13]
229238
; GFX10-NEXT: s_mov_b32 s3, s12
230239
; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0
231240
; GFX10-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
232241
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
233-
; GFX10-NEXT: s_mov_b32 s2, 1
234242
; GFX10-NEXT: v_mbcnt_hi_u32_b32 v1, -1, v1
235243
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1
236244
; GFX10-NEXT: v_and_b32_e32 v3, 1, v1
@@ -257,13 +265,12 @@ define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3
257265
; GFX10-NEXT: s_cbranch_vccnz .LBB4_2
258266
; GFX10-NEXT: ; %bb.3: ; %.preheader._crit_edge
259267
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v2
268+
; GFX10-NEXT: s_mov_b32 s13, 0
260269
; GFX10-NEXT: s_or_b32 s2, s0, vcc_lo
261270
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
262-
; GFX10-NEXT: s_mov_b32 s2, 0
263271
; GFX10-NEXT: .LBB4_4: ; %Flow
264-
; GFX10-NEXT: s_and_b32 s2, s2, 1
265-
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
266-
; GFX10-NEXT: s_cbranch_scc0 .LBB4_6
272+
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s13
273+
; GFX10-NEXT: s_cbranch_vccz .LBB4_6
267274
; GFX10-NEXT: ; %bb.5: ; %.19
268275
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
269276
; GFX10-NEXT: v_or_b32_e32 v3, 2, v1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
22
# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
33

4-
# Test is updated but copies between S1-register-with-reg-class and
5-
# register-with-reg-class-no-LLT fail machine verification
6-
# REQUIRES: do-not-run-me-with-machine-verifier
7-
84
--- |
95
define void @divergent_i1_phi_uniform_branch() {ret void}
106
define void @divergent_i1_phi_uniform_branch_simple() {ret void}
@@ -147,8 +143,8 @@ body: |
147143
; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
148144
; GFX10-NEXT: {{ $}}
149145
; GFX10-NEXT: bb.2:
150-
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[ICMP]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.1
151-
; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]]
146+
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[ICMP]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.1
147+
; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
152148
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
153149
; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
154150
; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY6]](s1), [[C4]], [[C3]]
@@ -206,11 +202,11 @@ body: |
206202
; GFX10-NEXT: bb.1:
207203
; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
208204
; GFX10-NEXT: {{ $}}
209-
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[DEF]](s1), %bb.0, %22(s1), %bb.1
205+
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %22(s1), %bb.1
210206
; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0
211207
; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1
212208
; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1
213-
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]]
209+
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
214210
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
215211
; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]
216212
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
@@ -301,11 +297,11 @@ body: |
301297
; GFX10-NEXT: bb.1:
302298
; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
303299
; GFX10-NEXT: {{ $}}
304-
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[DEF]](s1), %bb.0, %39(s1), %bb.5
300+
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %39(s1), %bb.5
305301
; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.5, [[C]](s32), %bb.0
306302
; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.5
307303
; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = G_PHI [[FCMP]](s1), %bb.0, %19(s1), %bb.5
308-
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]]
304+
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
309305
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
310306
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
311307
; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PHI2]](s32), [[C3]]

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