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dsandersllvmdsandersllvm
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[mips] EABI CodeGen is completely untested and seems to have bitrotted. Remove it.
Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658
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-69
lines changed

7 files changed

+3
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lines changed

‎llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
4242
unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
4343
if (IsO32())
4444
return CC != CallingConv::Fast ? 16 : 0;
45-
if (IsN32() || IsN64() || IsEABI())
45+
if (IsN32() || IsN64())
4646
return 0;
4747
llvm_unreachable("Unhandled ABI");
4848
}
@@ -55,8 +55,6 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
5555
return MipsABIInfo::N32();
5656
else if (Options.getABIName().startswith("n64"))
5757
return MipsABIInfo::N64();
58-
else if (Options.getABIName().startswith("eabi"))
59-
return MipsABIInfo::EABI();
6058
else if (!Options.getABIName().empty())
6159
llvm_unreachable("Unknown ABI option for MIPS");
6260

‎llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ class TargetRegisterClass;
2323

2424
class MipsABIInfo {
2525
public:
26-
enum class ABI { Unknown, O32, N32, N64, EABI };
26+
enum class ABI { Unknown, O32, N32, N64 };
2727

2828
protected:
2929
ABI ThisABI;
@@ -35,15 +35,13 @@ class MipsABIInfo {
3535
static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
3636
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
3737
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
38-
static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
3938
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
4039
const MCTargetOptions &Options);
4140

4241
bool IsKnown() const { return ThisABI != ABI::Unknown; }
4342
bool IsO32() const { return ThisABI == ABI::O32; }
4443
bool IsN32() const { return ThisABI == ABI::N32; }
4544
bool IsN64() const { return ThisABI == ABI::N64; }
46-
bool IsEABI() const { return ThisABI == ABI::EABI; }
4745
ABI GetEnumValue() const { return ThisABI; }
4846

4947
/// The registers to use for byval arguments.

‎llvm/lib/Target/Mips/MipsAsmPrinter.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -313,7 +313,6 @@ const char *MipsAsmPrinter::getCurrentABIString() const {
313313
case MipsABIInfo::ABI::O32: return "abi32";
314314
case MipsABIInfo::ABI::N32: return "abiN32";
315315
case MipsABIInfo::ABI::N64: return "abi64";
316-
case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
317316
default: llvm_unreachable("Unknown Mips ABI");
318317
}
319318
}
@@ -713,15 +712,6 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
713712

714713
// TODO: handle O64 ABI
715714

716-
if (ABI.IsEABI()) {
717-
if (STI.isGP32bit())
718-
OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long32",
719-
ELF::SHT_PROGBITS, 0));
720-
else
721-
OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long64",
722-
ELF::SHT_PROGBITS, 0));
723-
}
724-
725715
TS.updateABIInfo(STI);
726716

727717
// We should always emit a '.module fp=...' but binutils 2.24 does not accept

‎llvm/lib/Target/Mips/MipsCallingConv.td

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -211,48 +211,6 @@ def RetCC_MipsN : CallingConv<[
211211
CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
212212
]>;
213213

214-
//===----------------------------------------------------------------------===//
215-
// Mips EABI Calling Convention
216-
//===----------------------------------------------------------------------===//
217-
218-
def CC_MipsEABI : CallingConv<[
219-
// Promote i8/i16 arguments to i32.
220-
CCIfType<[i8, i16], CCPromoteToType<i32>>,
221-
222-
// Integer arguments are passed in integer registers.
223-
CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
224-
225-
// Single fp arguments are passed in pairs within 32-bit mode
226-
CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
227-
CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
228-
229-
CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
230-
CCAssignToReg<[F12, F14, F16, F18]>>>,
231-
232-
// The first 4 double fp arguments are passed in single fp registers.
233-
CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
234-
CCAssignToReg<[D6, D7, D8, D9]>>>,
235-
236-
// Integer values get stored in stack slots that are 4 bytes in
237-
// size and 4-byte aligned.
238-
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
239-
240-
// Integer values get stored in stack slots that are 8 bytes in
241-
// size and 8-byte aligned.
242-
CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
243-
]>;
244-
245-
def RetCC_MipsEABI : CallingConv<[
246-
// i32 are returned in registers V0, V1
247-
CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
248-
249-
// f32 are returned in registers F0, F1
250-
CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
251-
252-
// f64 are returned in register D0
253-
CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
254-
]>;
255-
256214
//===----------------------------------------------------------------------===//
257215
// Mips FastCC Calling Convention
258216
//===----------------------------------------------------------------------===//
@@ -325,7 +283,6 @@ def CC_Mips_FastCC : CallingConv<[
325283
// Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
326284
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
327285

328-
CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
329286
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
330287
CCDelegateTo<CC_MipsN_FastCC>
331288
]>;
@@ -335,7 +292,6 @@ def CC_Mips_FastCC : CallingConv<[
335292
//===----------------------------------------------------------------------===//
336293

337294
def RetCC_Mips : CallingConv<[
338-
CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
339295
CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
340296
CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
341297
CCDelegateTo<RetCC_MipsO32>
@@ -377,17 +333,13 @@ def CC_Mips_FixedArg : CallingConv<[
377333

378334
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
379335

380-
// FIXME: There wasn't an EABI case in the original code and it seems unlikely
381-
// that it's the same as CC_MipsN
382336
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
383337
CCDelegateTo<CC_MipsN>
384338
]>;
385339

386340
def CC_Mips_VarArg : CallingConv<[
387341
CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
388342

389-
// FIXME: There wasn't an EABI case in the original code and it seems unlikely
390-
// that it's the same as CC_MipsN_VarArg
391343
CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
392344
CCDelegateTo<CC_MipsN_VarArg>
393345
]>;

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2670,7 +2670,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
26702670
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
26712671
getPointerTy(DAG.getDataLayout()));
26722672

2673-
// With EABI is it possible to have 16 args on registers.
26742673
std::deque< std::pair<unsigned, SDValue> > RegsToPass;
26752674
SmallVector<SDValue, 8> MemOpChains;
26762675

‎llvm/lib/Target/Mips/MipsSubtarget.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
9090
report_fatal_error("Code generation for MIPS-V is not implemented", false);
9191

9292
// Check if Architecture and ABI are compatible.
93-
assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
93+
assert(((!isGP64bit() && isABI_O32()) ||
9494
(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
9595
"Invalid Arch & ABI pair.");
9696

@@ -164,7 +164,6 @@ Reloc::Model MipsSubtarget::getRelocationModel() const {
164164
return TM.getRelocationModel();
165165
}
166166

167-
bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
168167
bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
169168
bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
170169
bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }

‎llvm/lib/Target/Mips/MipsSubtarget.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -163,8 +163,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
163163
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
164164
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
165165

166-
/// Only O32 and EABI supported right now.
167-
bool isABI_EABI() const;
168166
bool isABI_N64() const;
169167
bool isABI_N32() const;
170168
bool isABI_O32() const;

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