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[ARM64EC] Warn on using disallowed registers in assembly src. (#93618)
ARM64EC designates a set of disallowed registers, because a mapping does not exist from them to x64. The MSVC assembler (armasm64) has a warning for this. A test is also included as part of the patch. See the list of disallowed registers below: https://learn.microsoft.com/en-us/cpp/build/arm64ec-windows-abi-conventions?view=msvc-170#register-mapping
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‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

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@@ -294,11 +294,13 @@ class AArch64AsmParser : public MCTargetAsmParser {
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#include "AArch64GenAsmMatcher.inc"
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};
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bool IsILP32;
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bool IsWindowsArm64EC;
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AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
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const MCInstrInfo &MII, const MCTargetOptions &Options)
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: MCTargetAsmParser(Options, STI, MII) {
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IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
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IsWindowsArm64EC = STI.getTargetTriple().isWindowsArm64EC();
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MCAsmParserExtension::Initialize(Parser);
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MCStreamer &S = getParser().getStreamer();
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if (S.getTargetStreamer() == nullptr)
@@ -5315,6 +5317,31 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
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}
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}
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// On ARM64EC, only valid registers may be used. Warn against using
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// explicitly disallowed registers.
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if (IsWindowsArm64EC) {
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for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
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if (Inst.getOperand(i).isReg()) {
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unsigned Reg = Inst.getOperand(i).getReg();
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// At this point, vector registers are matched to their
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// appropriately sized alias.
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if ((Reg == AArch64::W13 || Reg == AArch64::X13) ||
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(Reg == AArch64::W14 || Reg == AArch64::X14) ||
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(Reg == AArch64::W23 || Reg == AArch64::X23) ||
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(Reg == AArch64::W24 || Reg == AArch64::X24) ||
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(Reg == AArch64::W28 || Reg == AArch64::X28) ||
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(Reg >= AArch64::Q16 && Reg <= AArch64::Q31) ||
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(Reg >= AArch64::D16 && Reg <= AArch64::D31) ||
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(Reg >= AArch64::S16 && Reg <= AArch64::S31) ||
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(Reg >= AArch64::H16 && Reg <= AArch64::H31) ||
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(Reg >= AArch64::B16 && Reg <= AArch64::B31)) {
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Warning(IDLoc, "register " + Twine(RI->getName(Reg)) +
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" is disallowed on ARM64EC.");
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}
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}
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}
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}
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// Check for indexed addressing modes w/ the base register being the
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// same as a destination/source register or pair load where
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// the Rt == Rt2. All of those are undefined behaviour.

‎llvm/test/MC/AArch64/arm64ec-disallowed-regs.s

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@@ -0,0 +1,91 @@
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// RUN: llvm-mc -triple arm64ec-pc-windows-msvc < %s 2> %t.log
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// RUN: FileCheck %s --check-prefix=CHECK-ERR < %t.log
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// RUN: llvm-mc -triple aarch64-windows-msvc < %s > %t.log 2>&1
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// RUN: FileCheck %s --check-prefix=CHECK-NOEC < %t.log
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// ---- disallowed x registers ----
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orr x13, x0, x1 // x13
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// CHECK-ERR: warning: register X13 is disallowed on ARM64EC.
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orr x14, x2, x3 // x14
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// CHECK-ERR: warning: register X14 is disallowed on ARM64EC.
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orr x4, x23, x5 // x23
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// CHECK-ERR: warning: register X23 is disallowed on ARM64EC.
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orr x6, x7, x24 // x24
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// CHECK-ERR: warning: register X24 is disallowed on ARM64EC.
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orr x28, x8, x9 // x28
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// CHECK-ERR: warning: register X28 is disallowed on ARM64EC.
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// ---- disallowed w registers ----
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orr w0, w13, w1 // w13
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// CHECK-ERR: warning: register W13 is disallowed on ARM64EC.
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orr w14, w2, w3 // w14
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// CHECK-ERR: warning: register W14 is disallowed on ARM64EC.
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orr w4, w23, w5 // w23
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// CHECK-ERR: warning: register W23 is disallowed on ARM64EC.
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orr w6, w7, w24 // W24
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// CHECK-ERR: warning: register W24 is disallowed on ARM64EC.
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orr w28, w8, w9 // w28
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// CHECK-ERR: warning: register W28 is disallowed on ARM64EC.
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// ---- disallowed vector registers ----
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orn v1.8b, v16.8b, v2.8b // v16
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// CHECK-ERR: warning: register D16 is disallowed on ARM64EC.
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orn v2.16b, v17.16b, v3.16b // v17
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// CHECK-ERR: warning: register Q17 is disallowed on ARM64EC.
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orn v3.8b, v18.8b, v4.8b // v18
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// CHECK-ERR: warning: register D18 is disallowed on ARM64EC.
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orn v4.16b, v19.16b, v5.16b // v19
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// CHECK-ERR: warning: register Q19 is disallowed on ARM64EC.
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orn v5.8b, v20.8b, v6.8b // v20
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// CHECK-ERR: warning: register D20 is disallowed on ARM64EC.
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orn v21.8b, v6.8b, v7.8b // v21
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// CHECK-ERR: warning: register D21 is disallowed on ARM64EC.
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orn v7.16b, v8.16b, v22.16b // v22
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// CHECK-ERR: warning: register Q22 is disallowed on ARM64EC.
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orn v23.8b, v8.8b, v9.8b // v23
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// CHECK-ERR: warning: register D23 is disallowed on ARM64EC.
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orn v9.16b, v24.16b, v10.16b // v24
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// CHECK-ERR: warning: register Q24 is disallowed on ARM64EC.
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orn v10.8b, v25.8b, v11.8b // v25
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// CHECK-ERR: warning: register D25 is disallowed on ARM64EC.
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orn v11.8b, v12.8b, v26.8b // v26
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// CHECK-ERR: warning: register D26 is disallowed on ARM64EC.
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orn v12.8b, v27.8b, v13.8b // v27
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// CHECK-ERR: warning: register D27 is disallowed on ARM64EC.
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orn v13.16b, v28.16b, v14.16b // v28
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// CHECK-ERR: warning: register Q28 is disallowed on ARM64EC.
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orn v14.8b, v29.8b, v15.8b // v29
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// CHECK-ERR: warning: register D29 is disallowed on ARM64EC.
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orn v15.8b, v30.8b, v15.8b // v30
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// CHECK-ERR: warning: register D30 is disallowed on ARM64EC.
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orn v1.16b, v31.16b, v1.16b // v31
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// CHECK-ERR: warning: register Q31 is disallowed on ARM64EC.
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// ---- random tests on h, b, d, s registers ----
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orn.16b v1, v16, v2
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// CHECK-ERR: warning: register Q16 is disallowed on ARM64EC.
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str d17, [x0]
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// CHECK-ERR: warning: register D17 is disallowed on ARM64EC.
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fmul d2, d18, d11
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// CHECK-ERR: warning: register D18 is disallowed on ARM64EC.
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clz.8h v3, v19
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// CHECK-ERR: warning: register Q19 is disallowed on ARM64EC.
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add.4s v0, v20, v1
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// CHECK-ERR: warning: register Q20 is disallowed on ARM64EC.
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add.2d v0, v20, v1
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// CHECK-ERR: warning: register Q20 is disallowed on ARM64EC.
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str b17, [x28]
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// CHECK-ERR: warning: register B17 is disallowed on ARM64EC.
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// CHECK-ERR: warning: register X28 is disallowed on ARM64EC.
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addv h21, v22.4h
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// CHECK-ERR: warning: register H21 is disallowed on ARM64EC.
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// CHECK-ERR: warning: register D22 is disallowed on ARM64EC.
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mov w14, v24.s[0]
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// CHECK-ERR: warning: register W14 is disallowed on ARM64EC.
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// CHECK-ERR: warning: register Q24 is disallowed on ARM64EC.
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add x13, x14, x28
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// CHECK-ERR: warning: register X13 is disallowed on ARM64EC.
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// CHECK-ERR: warning: register X14 is disallowed on ARM64EC.
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// CHECK-ERR: warning: register X28 is disallowed on ARM64EC.
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// CHECK-NOEC-NOT: warning:

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