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findImplicitExecSrc -> findSetInactiveMask
1 parent 44afd5f commit 439661b

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3 files changed

+6
-4
lines changed

3 files changed

+6
-4
lines changed

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2098,7 +2098,9 @@ unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {
20982098
}
20992099
}
21002100

2101-
Register SIInstrInfo::findImplicitExecSrc(const MachineInstr &MI) {
2101+
Register SIInstrInfo::findSetInactiveMask(const MachineInstr &MI) {
2102+
assert(MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 ||
2103+
MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64);
21022104
for (auto &Op : MI.implicit_operands()) {
21032105
if (Op.isDef())
21042106
continue;
@@ -2298,7 +2300,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
22982300
MachineOperand &InactiveSrc = MI.getOperand(2);
22992301

23002302
// Find implicit register defining lanes active outside WWM.
2301-
Register ExecSrcReg = findImplicitExecSrc(MI);
2303+
Register ExecSrcReg = findSetInactiveMask(MI);
23022304
assert(ExecSrcReg && "V_SET_INACTIVE must be in known WWM region");
23032305
// Note: default here is set to ExecReg so that functional MIR is still
23042306
// generated if implicit def is not found and assertions are disabled.

llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1438,7 +1438,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
14381438
// regardless.
14391439
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
14401440

1441-
static Register findImplicitExecSrc(const MachineInstr &MI);
1441+
static Register findSetInactiveMask(const MachineInstr &MI);
14421442
};
14431443

14441444
/// \brief Returns true if a reg:subreg pair P has a TRC class

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,7 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
562562
// Ignore these if V_SET_INACTIVE which already has exec src register.
563563
// These are generated by an earlier pass which has seperately ensured
564564
// WWM and provided a mask of inactive lanes.
565-
Register ExecSrc = TII->findImplicitExecSrc(MI);
565+
Register ExecSrc = TII->findSetInactiveMask(MI);
566566
if (!ExecSrc) {
567567
// Disable strict states; StrictWQM will be added as required later.
568568
III.Disabled = StateStrict;

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