@@ -488,3 +488,69 @@ define <vscale x 1 x i32> @load_scalable_vector(i64 %y) nounwind {
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%3 = load <vscale x 1 x i32 >, ptr %2 , align 8
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ret <vscale x 1 x i32 > %3
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}
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+
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+ define void @scalable_alloca (i64 %y ) nounwind {
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+ ; CHECK-LABEL: @scalable_alloca(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8
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+ ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 5
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+ ; CHECK-NEXT: [[TMP4:%.*]] = alloca <vscale x 4 x i16>, i32 5, align 8
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+ ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 8
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+ ; CHECK-NEXT: [[DOTIDX:%.*]] = mul i64 [[Y:%.*]], [[TMP6]]
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+ ; CHECK-NEXT: [[TMP7:%.*]] = add i64 0, [[DOTIDX]]
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+ ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds <vscale x 4 x i16>, ptr [[TMP4]], i64 [[Y]]
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+ ; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
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+ ; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[TMP3]], [[TMP7]]
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+ ; CHECK-NEXT: [[TMP12:%.*]] = icmp ult i64 [[TMP3]], [[TMP7]]
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+ ; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i64 [[TMP11]], [[TMP10]]
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+ ; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[TMP13]]
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+ ; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i64 [[TMP7]], 0
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+ ; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
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+ ; CHECK-NEXT: br i1 [[TMP16]], label [[TRAP:%.*]], label [[TMP17:%.*]]
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+ ; CHECK: 17:
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+ ; CHECK-NEXT: [[TMP18:%.*]] = load <vscale x 4 x i16>, ptr [[TMP8]], align 4
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+ ; CHECK-NEXT: ret void
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+ ; CHECK: trap:
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+ ; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
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+ ; CHECK-NEXT: unreachable
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+ ;
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+ %1 = alloca <vscale x 4 x i16 >, i32 5
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+ %2 = getelementptr inbounds <vscale x 4 x i16 >, ptr %1 , i64 %y
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+ %3 = load <vscale x 4 x i16 >, ptr %2 , align 4
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+ ret void
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+ }
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+
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+ define void @scalable_alloca2 (i64 %y ) nounwind {
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+ ; CHECK-LABEL: @scalable_alloca2(
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+ ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 32
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+ ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 1
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+ ; CHECK-NEXT: [[TMP4:%.*]] = alloca <vscale x 4 x i64>, align 32
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+ ; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 32
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+ ; CHECK-NEXT: [[DOTIDX:%.*]] = mul i64 [[Y:%.*]], [[TMP6]]
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+ ; CHECK-NEXT: [[TMP7:%.*]] = add i64 0, [[DOTIDX]]
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+ ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds <vscale x 4 x i64>, ptr [[TMP4]], i64 [[Y]]
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+ ; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
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+ ; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 32
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+ ; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[TMP3]], [[TMP7]]
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+ ; CHECK-NEXT: [[TMP12:%.*]] = icmp ult i64 [[TMP3]], [[TMP7]]
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+ ; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i64 [[TMP11]], [[TMP10]]
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+ ; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[TMP13]]
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+ ; CHECK-NEXT: [[TMP15:%.*]] = icmp slt i64 [[TMP7]], 0
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+ ; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
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+ ; CHECK-NEXT: br i1 [[TMP16]], label [[TRAP:%.*]], label [[TMP17:%.*]]
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+ ; CHECK: 17:
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+ ; CHECK-NEXT: [[TMP18:%.*]] = load <vscale x 4 x i64>, ptr [[TMP8]], align 4
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+ ; CHECK-NEXT: ret void
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+ ; CHECK: trap:
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+ ; CHECK-NEXT: call void @llvm.trap() #[[ATTR6]]
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+ ; CHECK-NEXT: unreachable
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+ ;
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+ %1 = alloca <vscale x 4 x i64 >
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+ %2 = getelementptr inbounds <vscale x 4 x i64 >, ptr %1 , i64 %y
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+ %3 = load <vscale x 4 x i64 >, ptr %2 , align 4
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+ ret void
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+ }
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