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1 parent a27164c commit 43d207aCopy full SHA for 43d207a
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21785,7 +21785,7 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
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Op == Instruction::And || Op == Instruction::Or ||
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Op == Instruction::Xor || Op == Instruction::InsertElement ||
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Op == Instruction::ShuffleVector || Op == Instruction::Load ||
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- Op == Instruction::Freeze)
+ Op == Instruction::Freeze || Op == Instruction::Store)
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return false;
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if (Inst.getType()->isScalableTy())
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