Skip to content

Commit 43f01ed

Browse files
lialanlialan
committed
update comments
1 parent bb12265 commit 43f01ed

File tree

1 file changed

+122
-29
lines changed

1 file changed

+122
-29
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shifts.mir

Lines changed: 122 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s
33

44
---
55
name: combine_ashr
@@ -19,13 +19,13 @@ body: |
1919
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
2020
; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
2121
; CHECK-NEXT: SI_RETURN
22-
%9:_(s32) = COPY $vgpr0
23-
%10:_(s32) = COPY $vgpr1
24-
%0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
25-
%12:_(s32) = G_CONSTANT i32 10
26-
%11:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
27-
%13:_(s32) = G_ASHR %11, %12(s32)
28-
G_STORE %13(s32), %0(p0) :: (store (s32))
22+
%0:_(s32) = COPY $vgpr0
23+
%1:_(s32) = COPY $vgpr1
24+
%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
25+
%3:_(s32) = G_CONSTANT i32 10
26+
%4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
27+
%5:_(s32) = G_ASHR %4, %3(s32)
28+
G_STORE %5(s32), %2(p0) :: (store (s32))
2929
SI_RETURN
3030
3131
...
@@ -47,13 +47,13 @@ body: |
4747
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
4848
; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
4949
; CHECK-NEXT: SI_RETURN
50-
%9:_(s32) = COPY $vgpr0
51-
%10:_(s32) = COPY $vgpr1
52-
%0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
53-
%12:_(s32) = G_CONSTANT i32 10
54-
%11:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
55-
%13:_(s32) = G_LSHR %11, %12(s32)
56-
G_STORE %13(s32), %0(p0) :: (store (s32))
50+
%0:_(s32) = COPY $vgpr0
51+
%1:_(s32) = COPY $vgpr1
52+
%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
53+
%3:_(s32) = G_CONSTANT i32 10
54+
%4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
55+
%5:_(s32) = G_LSHR %4, %3(s32)
56+
G_STORE %5(s32), %2(p0) :: (store (s32))
5757
SI_RETURN
5858
5959
...
@@ -75,13 +75,13 @@ body: |
7575
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
7676
; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
7777
; CHECK-NEXT: SI_RETURN
78-
%9:_(s32) = COPY $vgpr0
79-
%10:_(s32) = COPY $vgpr1
80-
%0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
81-
%12:_(s32) = G_CONSTANT i32 16
82-
%11:_(s32) = G_CONSTANT i32 4294901760
83-
%13:_(s32) = G_SHL %11, %12(s32)
84-
G_STORE %13(s32), %0(p0) :: (store (s32))
78+
%0:_(s32) = COPY $vgpr0
79+
%1:_(s32) = COPY $vgpr1
80+
%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
81+
%3:_(s32) = G_CONSTANT i32 16
82+
%4:_(s32) = G_CONSTANT i32 4294901760
83+
%5:_(s32) = G_SHL %4, %3(s32)
84+
G_STORE %5(s32), %2(p0) :: (store (s32))
8585
SI_RETURN
8686
8787
...
@@ -103,13 +103,106 @@ body: |
103103
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
104104
; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p0) :: (store (s8))
105105
; CHECK-NEXT: SI_RETURN
106-
%9:_(s32) = COPY $vgpr0
107-
%10:_(s32) = COPY $vgpr1
108-
%0:_(p0) = G_MERGE_VALUES %9(s32), %10(s32)
109-
%12:_(s32) = G_CONSTANT i32 1
110-
%11:_(s8) = G_CONSTANT i8 -2
111-
%13:_(s8) = G_ASHR %11, %12(s32)
112-
G_STORE %13(s8), %0(p0) :: (store (s8))
106+
%0:_(s32) = COPY $vgpr0
107+
%1:_(s32) = COPY $vgpr1
108+
%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
109+
%3:_(s32) = G_CONSTANT i32 1
110+
%4:_(s8) = G_CONSTANT i8 -2
111+
%5:_(s8) = G_ASHR %4, %3(s32)
112+
G_STORE %5(s8), %2(p0) :: (store (s8))
113113
SI_RETURN
114114
115115
...
116+
---
117+
name: combine_vector_lshr
118+
tracksRegLiveness: true
119+
body: |
120+
bb.0:
121+
liveins: $vgpr0, $vgpr1, $vgpr31
122+
123+
liveins: $vgpr0, $vgpr1
124+
125+
; CHECK-LABEL: name: combine_vector_lshr
126+
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
129+
; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
130+
; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
131+
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
132+
%0:_(<2 x s32>) = G_IMPLICIT_DEF
133+
%1:_(s32) = G_CONSTANT i32 511
134+
%2:_(s32) = G_CONSTANT i32 0
135+
%3:_(s32) = G_CONSTANT i32 1
136+
%4:_(s32) = G_CONSTANT i32 9
137+
%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
138+
%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
139+
%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
140+
%8:_(<2 x s32>) = G_LSHR %7, %5(<2 x s32>)
141+
%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
142+
$vgpr0 = COPY %9(s32)
143+
$vgpr1 = COPY %10(s32)
144+
SI_RETURN implicit $vgpr0, implicit $vgpr1
145+
146+
...
147+
---
148+
name: combine_vector_shl
149+
tracksRegLiveness: true
150+
body: |
151+
bb.0:
152+
liveins: $vgpr0, $vgpr1, $vgpr31
153+
154+
liveins: $vgpr0, $vgpr1
155+
156+
; CHECK-LABEL: name: combine_vector_shl
157+
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
158+
; CHECK-NEXT: {{ $}}
159+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
160+
; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
161+
; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
162+
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
163+
%0:_(<2 x s32>) = G_IMPLICIT_DEF
164+
%1:_(s32) = G_CONSTANT i32 4294901760
165+
%2:_(s32) = G_CONSTANT i32 0
166+
%3:_(s32) = G_CONSTANT i32 1
167+
%4:_(s32) = G_CONSTANT i32 16
168+
%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
169+
%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
170+
%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
171+
%8:_(<2 x s32>) = G_SHL %7, %5(<2 x s32>)
172+
%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
173+
$vgpr0 = COPY %9(s32)
174+
$vgpr1 = COPY %10(s32)
175+
SI_RETURN implicit $vgpr0, implicit $vgpr1
176+
177+
...
178+
---
179+
name: combine_vector_ashr
180+
tracksRegLiveness: true
181+
body: |
182+
bb.0:
183+
liveins: $vgpr0, $vgpr1, $vgpr31
184+
185+
liveins: $vgpr0, $vgpr1
186+
187+
; CHECK-LABEL: name: combine_vector_ashr
188+
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
189+
; CHECK-NEXT: {{ $}}
190+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
191+
; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
192+
; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
193+
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
194+
%0:_(<2 x s32>) = G_IMPLICIT_DEF
195+
%1:_(s32) = G_CONSTANT i32 -1
196+
%2:_(s32) = G_CONSTANT i32 0
197+
%3:_(s32) = G_CONSTANT i32 1
198+
%4:_(s32) = G_CONSTANT i32 1
199+
%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
200+
%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
201+
%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
202+
%8:_(<2 x s32>) = G_ASHR %7, %5(<2 x s32>)
203+
%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
204+
$vgpr0 = COPY %9(s32)
205+
$vgpr1 = COPY %10(s32)
206+
SI_RETURN implicit $vgpr0, implicit $vgpr1
207+
208+
...

0 commit comments

Comments
 (0)