@@ -311,16 +311,15 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case TargetOpcode::G_LOAD: {
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LLT Ty = MRI.getType (MI.getOperand (0 ).getReg ());
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TypeSize Size = Ty.getSizeInBits ();
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- if (Ty.isVector ()) {
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+ if (Ty.isVector ())
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OpdsMapping[0 ] = getVRBValueMapping (Size.getKnownMinValue ());
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- OpdsMapping[1 ] = getVRBValueMapping (Size.getKnownMinValue ());
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- } else {
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+ else
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OpdsMapping[0 ] = GPRValueMapping;
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- OpdsMapping[ 1 ] = GPRValueMapping;
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- }
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+
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+ OpdsMapping[ 1 ] = GPRValueMapping;
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// Use FPR64 for s64 loads on rv32.
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if (!Ty.isVector () && GPRSize == 32 &&
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- Ty.getSizeInBits ().getKnownMinValue () == 64 ) {
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+ Ty.getSizeInBits ().getFixedValue () == 64 ) {
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assert (MF.getSubtarget <RISCVSubtarget>().hasStdExtD ());
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OpdsMapping[0 ] = getFPValueMapping (Ty.getSizeInBits ());
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break ;
@@ -341,17 +340,15 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case TargetOpcode::G_STORE: {
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LLT Ty = MRI.getType (MI.getOperand (0 ).getReg ());
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TypeSize Size = Ty.getSizeInBits ();
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- if (Ty.isVector ()) {
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+ if (Ty.isVector ())
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OpdsMapping[0 ] = getVRBValueMapping (Size.getKnownMinValue ());
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- OpdsMapping[1 ] = getVRBValueMapping (Size.getKnownMinValue ());
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- } else {
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+ else
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OpdsMapping[0 ] = GPRValueMapping;
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- OpdsMapping[1 ] = GPRValueMapping;
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- }
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+ OpdsMapping[1 ] = GPRValueMapping;
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// Use FPR64 for s64 stores on rv32.
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if (!Ty.isVector () && GPRSize == 32 &&
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- Ty.getSizeInBits ().getKnownMinValue () == 64 ) {
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+ Ty.getSizeInBits ().getFixedValue () == 64 ) {
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assert (MF.getSubtarget <RISCVSubtarget>().hasStdExtD ());
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OpdsMapping[0 ] = getFPValueMapping (Ty.getSizeInBits ());
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break ;
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