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michaelmaitlandmichaelmaitland
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[RISCV][GISel] Select G_SELECT (G_ICMP, A, B) (#68247)
If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst) as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 107 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#define DEBUG_TYPE "riscv-isel"
2727

2828
using namespace llvm;
29+
using namespace MIPatternMatch;
2930

3031
#define GET_GLOBALISEL_PREDICATE_BITSET
3132
#include "RISCVGenGlobalISel.inc"
@@ -83,6 +84,13 @@ class RISCVInstructionSelector : public InstructionSelector {
8384
void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
8485
int OpIdx) const;
8586

87+
/// Sets CC, LHS, and RHS so that they form an equivelent G_ICMP (ICMPCC, LHS,
88+
/// RHS) to that of MI, but whose condition code matches one of the
89+
/// comparisons supported directly by branches in the RISC-V ISA.
90+
void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
91+
MachineRegisterInfo &MRI, RISCVCC::CondCode &CC,
92+
Register &LHS, Register &RHS) const;
93+
8694
const RISCVSubtarget &STI;
8795
const RISCVInstrInfo &TII;
8896
const RISCVRegisterInfo &TRI;
@@ -498,21 +506,111 @@ bool RISCVInstructionSelector::selectSExtInreg(MachineInstr &MI,
498506
return true;
499507
}
500508

509+
/// Returns the RISCVCC::CondCode that corresponds to the CmpInst::Predicate CC.
510+
/// CC Must be an ICMP Predicate.
511+
static RISCVCC::CondCode getRISCVCCFromICMP(CmpInst::Predicate CC) {
512+
switch (CC) {
513+
default:
514+
llvm_unreachable("Expected ICMP CmpInst::Predicate.");
515+
case CmpInst::Predicate::ICMP_EQ:
516+
return RISCVCC::COND_EQ;
517+
case CmpInst::Predicate::ICMP_NE:
518+
return RISCVCC::COND_NE;
519+
case CmpInst::Predicate::ICMP_ULT:
520+
return RISCVCC::COND_LTU;
521+
case CmpInst::Predicate::ICMP_SLT:
522+
return RISCVCC::COND_LT;
523+
case CmpInst::Predicate::ICMP_UGE:
524+
return RISCVCC::COND_GEU;
525+
case CmpInst::Predicate::ICMP_SGE:
526+
return RISCVCC::COND_GE;
527+
}
528+
}
529+
530+
void RISCVInstructionSelector::getICMPOperandsForBranch(
531+
MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI,
532+
RISCVCC::CondCode &CC, Register &LHS, Register &RHS) const {
533+
assert(MI.getOpcode() == TargetOpcode::G_ICMP);
534+
CmpInst::Predicate ICMPCC =
535+
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
536+
LHS = MI.getOperand(2).getReg();
537+
RHS = MI.getOperand(3).getReg();
538+
539+
// Adjust comparisons to use comparison with 0 if possible.
540+
if (auto Constant = getIConstantVRegSExtVal(RHS, MRI, true)) {
541+
switch (ICMPCC) {
542+
case CmpInst::Predicate::ICMP_SGT:
543+
// Convert X > -1 to X >= 0
544+
if (*Constant == -1) {
545+
MachineInstr *Zero = MIB.buildConstant(MRI.getType(RHS), 0);
546+
selectConstant(*Zero, MIB, MRI);
547+
CC = RISCVCC::COND_GE;
548+
RHS = Zero->getOperand(0).getReg();
549+
return;
550+
}
551+
break;
552+
case CmpInst::Predicate::ICMP_SLT:
553+
// Convert X < 1 to 0 >= X
554+
if (*Constant == 1) {
555+
MachineInstr *Zero = MIB.buildConstant(MRI.getType(RHS), 0);
556+
selectConstant(*Zero, MIB, MRI);
557+
CC = RISCVCC::COND_GE;
558+
RHS = LHS;
559+
LHS = Zero->getOperand(0).getReg();
560+
return;
561+
}
562+
break;
563+
default:
564+
break;
565+
}
566+
}
567+
568+
switch (ICMPCC) {
569+
default:
570+
llvm_unreachable("Expected ICMP CmpInst::Predicate.");
571+
case CmpInst::Predicate::ICMP_EQ:
572+
case CmpInst::Predicate::ICMP_NE:
573+
case CmpInst::Predicate::ICMP_ULT:
574+
case CmpInst::Predicate::ICMP_SLT:
575+
case CmpInst::Predicate::ICMP_UGE:
576+
case CmpInst::Predicate::ICMP_SGE:
577+
// These CCs are supported directly by RISC-V branches.
578+
CC = getRISCVCCFromICMP(ICMPCC);
579+
return;
580+
case CmpInst::Predicate::ICMP_SGT:
581+
case CmpInst::Predicate::ICMP_SLE:
582+
case CmpInst::Predicate::ICMP_UGT:
583+
case CmpInst::Predicate::ICMP_ULE:
584+
// These CCs are not supported directly by RISC-V branches, but changing the
585+
// direction of the CC and swapping LHS and RHS are.
586+
CC = getRISCVCCFromICMP(CmpInst::getSwappedPredicate(ICMPCC));
587+
std::swap(LHS, RHS);
588+
return;
589+
}
590+
}
591+
501592
bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
502593
MachineIRBuilder &MIB,
503594
MachineRegisterInfo &MRI) const {
504-
// TODO: Currently we check that the conditional code passed to G_SELECT is
505-
// not equal to zero; however, in the future, we might want to try and check
506-
// if the conditional code comes from a G_ICMP. If it does, we can directly
507-
// use G_ICMP to get the first three input operands of the
508-
// Select_GPR_Using_CC_GPR. This might be done here, or in the appropriate
509-
// combiner.
510595
assert(MI.getOpcode() == TargetOpcode::G_SELECT);
596+
597+
// If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst)
598+
// as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
599+
Register MIOp1Reg = MI.getOperand(1).getReg();
600+
bool Op1IsICMP = mi_match(MIOp1Reg, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
601+
RISCVCC::CondCode CC;
602+
Register LHS, RHS;
603+
if (Op1IsICMP)
604+
getICMPOperandsForBranch(*MRI.getVRegDef(MIOp1Reg), MIB, MRI, CC, LHS, RHS);
605+
606+
Register Op1 = Op1IsICMP ? LHS : MI.getOperand(1).getReg();
607+
Register Op2 = Op1IsICMP ? RHS : RISCV::X0;
608+
unsigned Op3 = Op1IsICMP ? CC : RISCVCC::COND_NE;
511609
MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
512610
.addDef(MI.getOperand(0).getReg())
513-
.addReg(MI.getOperand(1).getReg())
514-
.addReg(RISCV::X0)
515-
.addImm(RISCVCC::COND_NE)
611+
.addReg(Op1)
612+
.addReg(Op2)
613+
.addImm(Op3)
516614
.addReg(MI.getOperand(2).getReg())
517615
.addReg(MI.getOperand(3).getReg());
518616
MI.eraseFromParent();

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv32.mir

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,3 +53,125 @@ body: |
5353
PseudoRET implicit $x10
5454
5555
...
56+
---
57+
name: select_icmp_ult
58+
legalized: true
59+
regBankSelected: true
60+
tracksRegLiveness: true
61+
body: |
62+
bb.0:
63+
liveins: $x10, $x11, $x12, $x13, $x14
64+
65+
; CHECK-LABEL: name: select_icmp_ult
66+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
67+
; CHECK-NEXT: {{ $}}
68+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
69+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
70+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
71+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
72+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 4, [[COPY]], [[COPY1]]
73+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
74+
; CHECK-NEXT: PseudoRET implicit $x10
75+
%0:gprb(s32) = COPY $x10
76+
%1:gprb(s32) = COPY $x11
77+
%2:gprb(s32) = COPY $x12
78+
%3:gprb(s32) = COPY $x13
79+
%4:gprb(s32) = COPY $x14
80+
%5:gprb(s32) = G_ICMP intpred(ult), %2, %3
81+
%6:gprb(s32) = G_SELECT %5, %0, %1
82+
$x10 = COPY %6(s32)
83+
PseudoRET implicit $x10
84+
85+
...
86+
---
87+
name: select_icmp_ugt
88+
legalized: true
89+
regBankSelected: true
90+
tracksRegLiveness: true
91+
body: |
92+
bb.0:
93+
liveins: $x10, $x11, $x12, $x13, $x14
94+
95+
; CHECK-LABEL: name: select_icmp_ugt
96+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
97+
; CHECK-NEXT: {{ $}}
98+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
99+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
100+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
101+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
102+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 4, [[COPY]], [[COPY1]]
103+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
104+
; CHECK-NEXT: PseudoRET implicit $x10
105+
%0:gprb(s32) = COPY $x10
106+
%1:gprb(s32) = COPY $x11
107+
%2:gprb(s32) = COPY $x12
108+
%3:gprb(s32) = COPY $x13
109+
%4:gprb(s32) = COPY $x14
110+
%5:gprb(s32) = G_ICMP intpred(ugt), %2, %3
111+
%6:gprb(s32) = G_SELECT %5, %0, %1
112+
$x10 = COPY %6(s32)
113+
PseudoRET implicit $x10
114+
115+
...
116+
---
117+
name: select_icmp_sgtneg1
118+
legalized: true
119+
regBankSelected: true
120+
tracksRegLiveness: true
121+
body: |
122+
bb.0:
123+
liveins: $x10, $x11, $x12, $x13, $x14
124+
125+
; CHECK-LABEL: name: select_icmp_sgtneg1
126+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
129+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
130+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
131+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
132+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 3, [[COPY]], [[COPY1]]
133+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
134+
; CHECK-NEXT: PseudoRET implicit $x10
135+
%0:gprb(s32) = COPY $x10
136+
%1:gprb(s32) = COPY $x11
137+
%2:gprb(s32) = COPY $x12
138+
%3:gprb(s32) = COPY $x13
139+
%4:gprb(s32) = COPY $x14
140+
%5:gprb(s32) = G_CONSTANT i32 -1
141+
%6:gprb(s32) = G_ICMP intpred(sgt), %2, %5
142+
%7:gprb(s32) = G_SELECT %6, %0, %1
143+
$x10 = COPY %7(s32)
144+
PseudoRET implicit $x10
145+
146+
...
147+
---
148+
name: select_icmp_slt1
149+
legalized: true
150+
regBankSelected: true
151+
tracksRegLiveness: true
152+
body: |
153+
bb.0:
154+
liveins: $x10, $x11, $x12, $x13, $x14
155+
156+
; CHECK-LABEL: name: select_icmp_slt1
157+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
158+
; CHECK-NEXT: {{ $}}
159+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
160+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
161+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
162+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
163+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 3, [[COPY]], [[COPY1]]
164+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
165+
; CHECK-NEXT: PseudoRET implicit $x10
166+
%0:gprb(s32) = COPY $x10
167+
%1:gprb(s32) = COPY $x11
168+
%2:gprb(s32) = COPY $x12
169+
%3:gprb(s32) = COPY $x13
170+
%4:gprb(s32) = COPY $x14
171+
%5:gprb(s32) = G_CONSTANT i32 1
172+
%6:gprb(s32) = G_ICMP intpred(slt), %2, %5
173+
%7:gprb(s32) = G_SELECT %6, %0, %1
174+
$x10 = COPY %7(s32)
175+
PseudoRET implicit $x10
176+
177+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,3 +53,125 @@ body: |
5353
PseudoRET implicit $x10
5454
5555
...
56+
---
57+
name: select_icmp_ult
58+
legalized: true
59+
regBankSelected: true
60+
tracksRegLiveness: true
61+
body: |
62+
bb.0:
63+
liveins: $x10, $x11, $x12, $x13, $x14
64+
65+
; CHECK-LABEL: name: select_icmp_ult
66+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
67+
; CHECK-NEXT: {{ $}}
68+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
69+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
70+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
71+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
72+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 4, [[COPY]], [[COPY1]]
73+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
74+
; CHECK-NEXT: PseudoRET implicit $x10
75+
%0:gprb(s64) = COPY $x10
76+
%1:gprb(s64) = COPY $x11
77+
%2:gprb(s64) = COPY $x12
78+
%3:gprb(s64) = COPY $x13
79+
%4:gprb(s64) = COPY $x14
80+
%5:gprb(s64) = G_ICMP intpred(ult), %2, %3
81+
%6:gprb(s64) = G_SELECT %5, %0, %1
82+
$x10 = COPY %6(s64)
83+
PseudoRET implicit $x10
84+
85+
...
86+
---
87+
name: select_icmp_ugt
88+
legalized: true
89+
regBankSelected: true
90+
tracksRegLiveness: true
91+
body: |
92+
bb.0:
93+
liveins: $x10, $x11, $x12, $x13, $x14
94+
95+
; CHECK-LABEL: name: select_icmp_ugt
96+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
97+
; CHECK-NEXT: {{ $}}
98+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
99+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
100+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
101+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
102+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 4, [[COPY]], [[COPY1]]
103+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
104+
; CHECK-NEXT: PseudoRET implicit $x10
105+
%0:gprb(s64) = COPY $x10
106+
%1:gprb(s64) = COPY $x11
107+
%2:gprb(s64) = COPY $x12
108+
%3:gprb(s64) = COPY $x13
109+
%4:gprb(s64) = COPY $x14
110+
%5:gprb(s64) = G_ICMP intpred(ugt), %2, %3
111+
%6:gprb(s64) = G_SELECT %5, %0, %1
112+
$x10 = COPY %6(s64)
113+
PseudoRET implicit $x10
114+
115+
...
116+
---
117+
name: select_icmp_sgtneg1
118+
legalized: true
119+
regBankSelected: true
120+
tracksRegLiveness: true
121+
body: |
122+
bb.0:
123+
liveins: $x10, $x11, $x12, $x13, $x14
124+
125+
; CHECK-LABEL: name: select_icmp_sgtneg1
126+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
129+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
130+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
131+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
132+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY2]], [[COPY3]], 3, [[COPY]], [[COPY1]]
133+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
134+
; CHECK-NEXT: PseudoRET implicit $x10
135+
%0:gprb(s64) = COPY $x10
136+
%1:gprb(s64) = COPY $x11
137+
%2:gprb(s64) = COPY $x12
138+
%3:gprb(s64) = COPY $x13
139+
%4:gprb(s64) = COPY $x14
140+
%5:gprb(s64) = G_CONSTANT i64 -1
141+
%6:gprb(s64) = G_ICMP intpred(sgt), %2, %5
142+
%7:gprb(s64) = G_SELECT %6, %0, %1
143+
$x10 = COPY %7(s64)
144+
PseudoRET implicit $x10
145+
146+
...
147+
---
148+
name: select_icmp_slt1
149+
legalized: true
150+
regBankSelected: true
151+
tracksRegLiveness: true
152+
body: |
153+
bb.0:
154+
liveins: $x10, $x11, $x12, $x13, $x14
155+
156+
; CHECK-LABEL: name: select_icmp_slt1
157+
; CHECK: liveins: $x10, $x11, $x12, $x13, $x14
158+
; CHECK-NEXT: {{ $}}
159+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
160+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
161+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
162+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
163+
; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY3]], [[COPY2]], 3, [[COPY]], [[COPY1]]
164+
; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]]
165+
; CHECK-NEXT: PseudoRET implicit $x10
166+
%0:gprb(s64) = COPY $x10
167+
%1:gprb(s64) = COPY $x11
168+
%2:gprb(s64) = COPY $x12
169+
%3:gprb(s64) = COPY $x13
170+
%4:gprb(s64) = COPY $x14
171+
%5:gprb(s64) = G_CONSTANT i64 1
172+
%6:gprb(s64) = G_ICMP intpred(slt), %2, %5
173+
%7:gprb(s64) = G_SELECT %6, %0, %1
174+
$x10 = COPY %7(s64)
175+
PseudoRET implicit $x10
176+
177+
...

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