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XinWang10 · XinWang10 · commit 44ad42ee7953 · 2023-12-05T22:45:44.000-08:00
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -680,10 +680,9 @@ def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
                   "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
                   Requires<[In64BitMode, HasINVPCID]>;
 
-let CD8_Scale = 0 in
 def INVPCID64_EVEX : I<0xF2, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
                        "invpcid\t{$src2, $src1|$src1, $src2}", []>,
-                     EVEX, T_MAP4XS, Requires<[In64BitMode, HasINVPCID]>;
+                     EVEX_NoCD8, T_MAP4XS, Requires<[In64BitMode, HasINVPCID]>;
 } // SchedRW
 
 let Predicates = [In64BitMode, HasINVPCID] in {
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -86,6 +86,7 @@ class EVEX_CD8<int esize, CD8VForm form> {
   int CD8_EltSize = !srl(esize, 3);
   bits<3> CD8_Form = form.Value;
 }
+class EVEX_NoCD8 : EVEX { bits<7> CD8_Scale = 0; }
 class XOP { Encoding OpEnc = EncXOP; }
 class XOP_4V : XOP { bit hasVEX_4V = 1; }
 class EVEX2VEXOverride<string VEXInstrName> {

Original file line number	Diff line number	Diff line change
`@@ -86,6 +86,7 @@ class EVEX_CD8<int esize, CD8VForm form> {`
`86`	`86`	`int CD8_EltSize = !srl(esize, 3);`
`87`	`87`	`bits<3> CD8_Form = form.Value;`
`88`	`88`	`}`
	`89`	`+class EVEX_NoCD8 : EVEX { bits<7> CD8_Scale = 0; }`
`89`	`90`	`class XOP { Encoding OpEnc = EncXOP; }`
`90`	`91`	`class XOP_4V : XOP { bit hasVEX_4V = 1; }`
`91`	`92`	`class EVEX2VEXOverride<string VEXInstrName> {`