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AMDGPU: Replace insertelement poison with insertelement undef
This is the bulk update with perl, with cases which require additional update left for later.
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136 files changed

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‎llvm/test/CodeGen/AMDGPU/add3.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
181181
%inner = add i32 %a, %b
182182
%outer = add i32 %inner, %c
183183
%x1 = mul i32 %outer, %x
184-
%r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
184+
%r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
185185
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
186186
%bc = bitcast <2 x i32> %r0 to <2 x float>
187187
ret <2 x float> %bc
@@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
207207
; GFX10-NEXT: ; return to shader part epilog
208208
%inner = add i32 %a, %b
209209
%outer = add i32 %inner, %c
210-
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
210+
%r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
211211
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
212212
%bc = bitcast <2 x i32> %r0 to <2 x float>
213213
ret <2 x float> %bc

‎llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
1717

1818
.beginls: ; preds = %.entry
1919
%tmp15 = extractelement <6 x i32> %arg8, i32 3
20-
%.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
20+
%.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
2121
%.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
2222
%tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
2323
br label %.endls

‎llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ bb:
3636
%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
3737
%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
3838
%tmp24 = extractelement <16 x i8> %tmp23, i64 3
39-
%tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
39+
%tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
4040
%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
4141
%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
4242
%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5

‎llvm/test/CodeGen/AMDGPU/anyext.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
187187
; GFX9-NEXT: s_endpgm
188188
bb:
189189
%tmp = load i16, ptr addrspace(1) undef, align 2
190-
%tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
190+
%tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
191191
%tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
192192
%tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
193193
%tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>

‎llvm/test/CodeGen/AMDGPU/bf16-conversions.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
189189
entry:
190190
%a.cvt = fptrunc float %a to bfloat
191191
%b.cvt = fptrunc float %b to bfloat
192-
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
192+
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
193193
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
194194
%ret = bitcast <2 x bfloat> %v2.2 to float
195195
ret float %ret
@@ -226,7 +226,7 @@ entry:
226226
%a.cvt = fptrunc float %a.neg to bfloat
227227
%b.abs = call float @llvm.fabs.f32(float %b)
228228
%b.cvt = fptrunc float %b.abs to bfloat
229-
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
229+
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
230230
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
231231
%ret = bitcast <2 x bfloat> %v2.2 to float
232232
ret float %ret

‎llvm/test/CodeGen/AMDGPU/bfi_nested.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
297297
; GCN-NEXT: s_endpgm
298298
%shift = lshr i32 %b, 16
299299
%tr = trunc i32 %shift to i16
300-
%tmp = insertelement <2 x i16> undef, i16 %a, i32 0
300+
%tmp = insertelement <2 x i16> poison, i16 %a, i32 0
301301
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
302302
%val = bitcast <2 x i16> %vec to i32
303303
store i32 %val, ptr addrspace(1) %out, align 4

‎llvm/test/CodeGen/AMDGPU/big_alu.ll

Lines changed: 90 additions & 90 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,9 @@ bb1789: ; preds = %bb1750
4848
%i1883 = shufflevector <3 x i32> %i1882, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
4949
%i1884 = bitcast <4 x i32> %i1883 to <4 x float>
5050
%i1885 = shufflevector <4 x float> %i1884, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
51-
%i1886 = insertelement <3 x i32> undef, i32 %i1819, i64 0
51+
%i1886 = insertelement <3 x i32> poison, i32 %i1819, i64 0
5252
%i1887 = bitcast <3 x i32> %i1886 to <3 x float>
53-
%i1888 = insertelement <3 x i32> undef, i32 %i1801, i64 0
53+
%i1888 = insertelement <3 x i32> poison, i32 %i1801, i64 0
5454
%i1889 = bitcast <3 x i32> %i1888 to <3 x float>
5555
%i1890 = fmul reassoc nnan nsz arcp contract afn <3 x float> %i1887, %i1889
5656
%i1891 = shufflevector <3 x float> %i1890, <3 x float> poison, <3 x i32> zeroinitializer

‎llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -15,15 +15,15 @@ entry:
1515
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
1616
%tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
1717
%tmp5 = extractelement <3 x double> %tmp4, i32 1
18-
%tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
19-
%tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
18+
%tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
19+
%tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
2020
%tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
2121
%tmp9 = extractelement <3 x double> %tmp8, i32 2
22-
%tmp10 = insertelement <3 x double> undef, double %tmp9, i32 2
22+
%tmp10 = insertelement <3 x double> poison, double %tmp9, i32 2
2323
%tmp11 = fcmp olt <3 x double> %tmp10, %tmp7
2424
%tmp12 = select <3 x i1> %tmp11, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
2525
%tmp13 = extractelement <3 x double> %tmp12, i64 1
26-
%tmp14 = insertelement <2 x double> undef, double %tmp13, i32 1
26+
%tmp14 = insertelement <2 x double> poison, double %tmp13, i32 1
2727
store <2 x double> %tmp14, ptr addrspace(1) undef, align 8, !tbaa !6
2828
ret void
2929
}
@@ -42,12 +42,12 @@ entry:
4242
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
4343
%tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
4444
%tmp5 = extractelement <3 x double> %tmp4, i32 1
45-
%tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
46-
%tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
45+
%tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
46+
%tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
4747
%tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
4848
%tmp9 = extractelement <3 x double> %tmp8, i32 1
49-
%tmp10 = insertelement <3 x double> undef, double %tmp9, i32 1
50-
%tmp11 = insertelement <3 x double> %tmp10, double undef, i32 2
49+
%tmp10 = insertelement <3 x double> poison, double %tmp9, i32 1
50+
%tmp11 = insertelement <3 x double> %tmp10, double poison, i32 2
5151
%tmp12 = fcmp olt <3 x double> %tmp11, %tmp7
5252
%tmp13 = select <3 x i1> %tmp12, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
5353
%tmp14 = extractelement <3 x double> %tmp13, i64 2

‎llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ bb1:
1515
%tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ]
1616
%tmp3 = load volatile half, ptr null, align 536870912
1717
%tmp4 = bitcast half %tmp3 to i16
18-
%tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1
18+
%tmp5 = insertelement <2 x i16> <i16 0, i16 poison>, i16 %tmp4, i32 1
1919
store volatile half %tmp2, ptr %arg, align 2
2020
%tmp7 = bitcast <2 x i16> %tmp to <2 x half>
2121
%tmp8 = extractelement <2 x half> %tmp7, i32 0

‎llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ define void @undef_lo_v2i16(i16 %arg0) {
2020
; GFX8-NEXT: ; use v0
2121
; GFX8-NEXT: ;;#ASMEND
2222
; GFX8-NEXT: s_setpc_b64 s[30:31]
23-
%undef.lo = insertelement <2 x i16> undef, i16 %arg0, i32 1
23+
%undef.lo = insertelement <2 x i16> poison, i16 %arg0, i32 1
2424
call void asm sideeffect "; use $0", "v"(<2 x i16> %undef.lo);
2525
ret void
2626
}
@@ -43,7 +43,7 @@ define void @undef_lo_v2f16(half %arg0) {
4343
; GFX8-NEXT: ; use v0
4444
; GFX8-NEXT: ;;#ASMEND
4545
; GFX8-NEXT: s_setpc_b64 s[30:31]
46-
%undef.lo = insertelement <2 x half> undef, half %arg0, i32 1
46+
%undef.lo = insertelement <2 x half> poison, half %arg0, i32 1
4747
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.lo);
4848
ret void
4949
}
@@ -69,7 +69,7 @@ define void @undef_lo_op_v2f16(half %arg0) {
6969
; GFX8-NEXT: ; use v0
7070
; GFX8-NEXT: ;;#ASMEND
7171
; GFX8-NEXT: s_setpc_b64 s[30:31]
72-
%undef.lo = insertelement <2 x half> undef, half %arg0, i32 1
72+
%undef.lo = insertelement <2 x half> poison, half %arg0, i32 1
7373
%op = fadd <2 x half> %undef.lo, <half 1.0, half 1.0>
7474
call void asm sideeffect "; use $0", "v"(<2 x half> %op);
7575
ret void
@@ -96,7 +96,7 @@ define void @undef_lo_op_v2i16(i16 %arg0) {
9696
; GFX8-NEXT: ; use v0
9797
; GFX8-NEXT: ;;#ASMEND
9898
; GFX8-NEXT: s_setpc_b64 s[30:31]
99-
%undef.lo = insertelement <2 x i16> undef, i16 %arg0, i32 1
99+
%undef.lo = insertelement <2 x i16> poison, i16 %arg0, i32 1
100100
%op = add <2 x i16> %undef.lo, <i16 99, i16 99>
101101
call void asm sideeffect "; use $0", "v"(<2 x i16> %op);
102102
ret void
@@ -120,7 +120,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
120120
; GFX8-NEXT: ; use v[0:1]
121121
; GFX8-NEXT: ;;#ASMEND
122122
; GFX8-NEXT: s_setpc_b64 s[30:31]
123-
%undef.lo = insertelement <4 x i16> undef, i16 %arg0, i32 1
123+
%undef.lo = insertelement <4 x i16> poison, i16 %arg0, i32 1
124124
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.lo);
125125
ret void
126126
}
@@ -143,7 +143,7 @@ define void @undef_lo3_v4f16(half %arg0) {
143143
; GFX8-NEXT: ; use v[0:1]
144144
; GFX8-NEXT: ;;#ASMEND
145145
; GFX8-NEXT: s_setpc_b64 s[30:31]
146-
%undef.lo = insertelement <4 x half> undef, half %arg0, i32 1
146+
%undef.lo = insertelement <4 x half> poison, half %arg0, i32 1
147147
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.lo);
148148
ret void
149149
}
@@ -214,7 +214,7 @@ define void @undef_hi_v2i16(i16 %arg0) {
214214
; GFX8-NEXT: ; use v0
215215
; GFX8-NEXT: ;;#ASMEND
216216
; GFX8-NEXT: s_setpc_b64 s[30:31]
217-
%undef.hi = insertelement <2 x i16> undef, i16 %arg0, i32 0
217+
%undef.hi = insertelement <2 x i16> poison, i16 %arg0, i32 0
218218
call void asm sideeffect "; use $0", "v"(<2 x i16> %undef.hi);
219219
ret void
220220
}
@@ -235,7 +235,7 @@ define void @undef_hi_v2f16(half %arg0) {
235235
; GFX8-NEXT: ; use v0
236236
; GFX8-NEXT: ;;#ASMEND
237237
; GFX8-NEXT: s_setpc_b64 s[30:31]
238-
%undef.hi = insertelement <2 x half> undef, half %arg0, i32 0
238+
%undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
239239
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.hi);
240240
ret void
241241
}
@@ -259,7 +259,7 @@ define void @undef_hi_op_v2f16(half %arg0) {
259259
; GFX8-NEXT: ; use v0
260260
; GFX8-NEXT: ;;#ASMEND
261261
; GFX8-NEXT: s_setpc_b64 s[30:31]
262-
%undef.hi = insertelement <2 x half> undef, half %arg0, i32 0
262+
%undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
263263
%op = fadd <2 x half> %undef.hi, <half 1.0, half 1.0>
264264
call void asm sideeffect "; use $0", "v"(<2 x half> %op);
265265
ret void
@@ -284,7 +284,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
284284
; GFX8-NEXT: ; use v0
285285
; GFX8-NEXT: ;;#ASMEND
286286
; GFX8-NEXT: s_setpc_b64 s[30:31]
287-
%undef.hi = insertelement <2 x i16> undef, i16 %arg0, i32 0
287+
%undef.hi = insertelement <2 x i16> poison, i16 %arg0, i32 0
288288
%op = add <2 x i16> %undef.hi, <i16 99, i16 99>
289289
call void asm sideeffect "; use $0", "v"(<2 x i16> %op);
290290
ret void
@@ -306,7 +306,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
306306
; GFX8-NEXT: ; use v[0:1]
307307
; GFX8-NEXT: ;;#ASMEND
308308
; GFX8-NEXT: s_setpc_b64 s[30:31]
309-
%undef.hi = insertelement <4 x i16> undef, i16 %arg0, i32 0
309+
%undef.hi = insertelement <4 x i16> poison, i16 %arg0, i32 0
310310
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.hi);
311311
ret void
312312
}
@@ -327,7 +327,7 @@ define void @undef_hi3_v4f16(half %arg0) {
327327
; GFX8-NEXT: ; use v[0:1]
328328
; GFX8-NEXT: ;;#ASMEND
329329
; GFX8-NEXT: s_setpc_b64 s[30:31]
330-
%undef.hi = insertelement <4 x half> undef, half %arg0, i32 0
330+
%undef.hi = insertelement <4 x half> poison, half %arg0, i32 0
331331
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.hi);
332332
ret void
333333
}

‎llvm/test/CodeGen/AMDGPU/build_vector-r600.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
7272
; R600-NEXT: 327680(4.591775e-40), 2(2.802597e-45)
7373
%srl = lshr i32 %a, 16
7474
%trunc = trunc i32 %srl to i16
75-
%ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
75+
%ins.0 = insertelement <2 x i16> poison, i16 %trunc, i32 0
7676
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
7777
store <2 x i16> %ins.1, ptr addrspace(1) %out
7878
ret void

‎llvm/test/CodeGen/AMDGPU/build_vector.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
245245
; GFX942-NEXT: s_endpgm
246246
%srl = lshr i32 %a, 16
247247
%trunc = trunc i32 %srl to i16
248-
%ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
248+
%ins.0 = insertelement <2 x i16> poison, i16 %trunc, i32 0
249249
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
250250
store <2 x i16> %ins.1, ptr addrspace(1) %out
251251
ret void

‎llvm/test/CodeGen/AMDGPU/bypass-div.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -860,7 +860,7 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
860860
; GFX9-NEXT: s_setpc_b64 s[30:31]
861861
%d = sdiv i64 %a, %b
862862
%r = srem i64 %a, %b
863-
%ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
863+
%ins.0 = insertelement <2 x i64> poison, i64 %d, i32 0
864864
%ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
865865
ret <2 x i64> %ins.1
866866
}
@@ -1012,7 +1012,7 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) {
10121012
; GFX9-NEXT: s_setpc_b64 s[30:31]
10131013
%d = udiv i64 %a, %b
10141014
%r = urem i64 %a, %b
1015-
%ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
1015+
%ins.0 = insertelement <2 x i64> poison, i64 %d, i32 0
10161016
%ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
10171017
ret <2 x i64> %ins.1
10181018
}

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