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[AArch64][GlobalISel] Legalize G_VECREDUCE_{MIN/MAX} (#69461)
Legalizes G_VECREDUCE_{MIN/MAX} and selects instructions for vecreduce_{min/max}
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6 files changed

+2119
-171
lines changed

6 files changed

+2119
-171
lines changed

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

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@@ -173,6 +173,10 @@ def : GINodeEquiv<G_VECREDUCE_FMAX, vecreduce_fmax>;
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def : GINodeEquiv<G_VECREDUCE_FMIN, vecreduce_fmin>;
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def : GINodeEquiv<G_VECREDUCE_FMAXIMUM, vecreduce_fmaximum>;
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def : GINodeEquiv<G_VECREDUCE_FMINIMUM, vecreduce_fminimum>;
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def : GINodeEquiv<G_VECREDUCE_UMIN, vecreduce_umin>;
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def : GINodeEquiv<G_VECREDUCE_UMAX, vecreduce_umax>;
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def : GINodeEquiv<G_VECREDUCE_SMIN, vecreduce_smin>;
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def : GINodeEquiv<G_VECREDUCE_SMAX, vecreduce_smax>;
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def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
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def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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@@ -6702,6 +6702,43 @@ defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
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def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
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(UMINPv2i32 V64:$Rn, V64:$Rn)>;
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// For vecreduce_{opc} used by GlobalISel, not SDAG at the moment
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// because GlobalISel allows us to specify the return register to be a FPR
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multiclass SIMDAcrossLanesVecReductionIntrinsic<string baseOpc,
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SDPatternOperator opNode> {
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def : Pat<(i8 (opNode (v8i8 FPR64:$Rn))),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) FPR64:$Rn)>;
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def : Pat<(i8 (opNode (v16i8 FPR128:$Rn))),
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(!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) FPR128:$Rn)>;
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def : Pat<(i16 (opNode (v4i16 FPR64:$Rn))),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) FPR64:$Rn)>;
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def : Pat<(i16 (opNode (v8i16 FPR128:$Rn))),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) FPR128:$Rn)>;
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def : Pat<(i32 (opNode (v4i32 V128:$Rn))),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn)>;
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}
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// For v2i32 source type, the pairwise instruction can be used instead
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defm : SIMDAcrossLanesVecReductionIntrinsic<"UMINV", vecreduce_umin>;
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def : Pat<(i32 (vecreduce_umin (v2i32 V64:$Rn))),
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(i32 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;
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defm : SIMDAcrossLanesVecReductionIntrinsic<"UMAXV", vecreduce_umax>;
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def : Pat<(i32 (vecreduce_umax (v2i32 V64:$Rn))),
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(i32 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;
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defm : SIMDAcrossLanesVecReductionIntrinsic<"SMINV", vecreduce_smin>;
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def : Pat<(i32 (vecreduce_smin (v2i32 V64:$Rn))),
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(i32 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;
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defm : SIMDAcrossLanesVecReductionIntrinsic<"SMAXV", vecreduce_smax>;
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def : Pat<(i32 (vecreduce_smax (v2i32 V64:$Rn))),
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(i32 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub))>;
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multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
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def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
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(i32 (SMOVvi16to32

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

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@@ -990,6 +990,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.scalarize(1)
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.lower();
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getActionDefinitionsBuilder(
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{G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX})
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.legalFor({{s8, v8s8},
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{s8, v16s8},
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{s16, v4s16},
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{s16, v8s16},
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{s32, v2s32},
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{s32, v4s32}})
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.clampMaxNumElements(1, s64, 2)
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.clampMaxNumElements(1, s32, 4)
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.clampMaxNumElements(1, s16, 8)
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.clampMaxNumElements(1, s8, 16)
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.scalarize(1)
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.lower();
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getActionDefinitionsBuilder(
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{G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
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// Try to break down into smaller vectors as long as they're at least 64

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -769,17 +769,20 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_VECREDUCE_SMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_VECREDUCE_SMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_VECREDUCE_UMAX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_VECREDUCE_UMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_SBFX (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK

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