Skip to content

Commit 4569cdb

Browse files
topperctopperc
committed
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types.
We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
1 parent 91ea992 commit 4569cdb

File tree

2 files changed

+108
-7
lines changed

2 files changed

+108
-7
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1445,6 +1445,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14451445
setOperationAction(ISD::FTRUNC, VT, Legal);
14461446
setOperationAction(ISD::FRINT, VT, Legal);
14471447
setOperationAction(ISD::FNEARBYINT, VT, Legal);
1448+
1449+
setOperationAction(ISD::SELECT, VT, Custom);
14481450
}
14491451

14501452
// Without BWI we need to use custom lowering to handle MVT::v64i8 input.
@@ -1464,13 +1466,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14641466
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
14651467
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
14661468

1467-
setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1468-
setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1469-
setOperationAction(ISD::SELECT, MVT::v16i32, Custom);
1470-
setOperationAction(ISD::SELECT, MVT::v32i16, Custom);
1471-
setOperationAction(ISD::SELECT, MVT::v64i8, Custom);
1472-
setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1473-
14741469
for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
14751470
setOperationAction(ISD::SMAX, VT, Legal);
14761471
setOperationAction(ISD::UMAX, VT, Legal);
@@ -1484,6 +1479,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14841479
setOperationAction(ISD::ROTL, VT, Custom);
14851480
setOperationAction(ISD::ROTR, VT, Custom);
14861481
setOperationAction(ISD::SETCC, VT, Custom);
1482+
setOperationAction(ISD::SELECT, VT, Custom);
14871483

14881484
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
14891485
// setcc all the way to isel and prefer SETGT in some isel patterns.
@@ -1704,6 +1700,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
17041700
setOperationAction(ISD::SADDSAT, VT, Legal);
17051701
setOperationAction(ISD::USUBSAT, VT, Legal);
17061702
setOperationAction(ISD::SSUBSAT, VT, Legal);
1703+
setOperationAction(ISD::SELECT, VT, Custom);
17071704

17081705
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
17091706
// setcc all the way to isel and prefer SETGT in some isel patterns.

‎llvm/test/CodeGen/X86/avx512-select.ll

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -433,3 +433,107 @@ define <16 x i16> @pr31515(<16 x i1> %a, <16 x i1> %b, <16 x i16> %c) nounwind {
433433
ret <16 x i16> %res
434434
}
435435

436+
define <32 x i16> @pr42355_v32i16(i1 %c, <32 x i16> %x, <32 x i16> %y) {
437+
; X86-AVX512F-LABEL: pr42355_v32i16:
438+
; X86-AVX512F: # %bb.0:
439+
; X86-AVX512F-NEXT: pushl %ebp
440+
; X86-AVX512F-NEXT: .cfi_def_cfa_offset 8
441+
; X86-AVX512F-NEXT: .cfi_offset %ebp, -8
442+
; X86-AVX512F-NEXT: movl %esp, %ebp
443+
; X86-AVX512F-NEXT: .cfi_def_cfa_register %ebp
444+
; X86-AVX512F-NEXT: andl $-32, %esp
445+
; X86-AVX512F-NEXT: subl $32, %esp
446+
; X86-AVX512F-NEXT: testb $1, 8(%ebp)
447+
; X86-AVX512F-NEXT: jne .LBB14_2
448+
; X86-AVX512F-NEXT: # %bb.1:
449+
; X86-AVX512F-NEXT: vmovaps 40(%ebp), %ymm1
450+
; X86-AVX512F-NEXT: vmovaps %ymm2, %ymm0
451+
; X86-AVX512F-NEXT: .LBB14_2:
452+
; X86-AVX512F-NEXT: movl %ebp, %esp
453+
; X86-AVX512F-NEXT: popl %ebp
454+
; X86-AVX512F-NEXT: .cfi_def_cfa %esp, 4
455+
; X86-AVX512F-NEXT: retl
456+
;
457+
; X64-AVX512F-LABEL: pr42355_v32i16:
458+
; X64-AVX512F: # %bb.0:
459+
; X64-AVX512F-NEXT: testb $1, %dil
460+
; X64-AVX512F-NEXT: jne .LBB14_2
461+
; X64-AVX512F-NEXT: # %bb.1:
462+
; X64-AVX512F-NEXT: vmovaps %ymm2, %ymm0
463+
; X64-AVX512F-NEXT: vmovaps %ymm3, %ymm1
464+
; X64-AVX512F-NEXT: .LBB14_2:
465+
; X64-AVX512F-NEXT: retq
466+
;
467+
; X86-AVX512BW-LABEL: pr42355_v32i16:
468+
; X86-AVX512BW: # %bb.0:
469+
; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp)
470+
; X86-AVX512BW-NEXT: jne .LBB14_2
471+
; X86-AVX512BW-NEXT: # %bb.1:
472+
; X86-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
473+
; X86-AVX512BW-NEXT: .LBB14_2:
474+
; X86-AVX512BW-NEXT: retl
475+
;
476+
; X64-AVX512BW-LABEL: pr42355_v32i16:
477+
; X64-AVX512BW: # %bb.0:
478+
; X64-AVX512BW-NEXT: testb $1, %dil
479+
; X64-AVX512BW-NEXT: jne .LBB14_2
480+
; X64-AVX512BW-NEXT: # %bb.1:
481+
; X64-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
482+
; X64-AVX512BW-NEXT: .LBB14_2:
483+
; X64-AVX512BW-NEXT: retq
484+
%a = select i1 %c, <32 x i16> %x, <32 x i16> %y
485+
ret <32 x i16> %a
486+
}
487+
488+
define <64 x i8> @pr42355_v64i8(i1 %c, <64 x i8> %x, <64 x i8> %y) {
489+
; X86-AVX512F-LABEL: pr42355_v64i8:
490+
; X86-AVX512F: # %bb.0:
491+
; X86-AVX512F-NEXT: pushl %ebp
492+
; X86-AVX512F-NEXT: .cfi_def_cfa_offset 8
493+
; X86-AVX512F-NEXT: .cfi_offset %ebp, -8
494+
; X86-AVX512F-NEXT: movl %esp, %ebp
495+
; X86-AVX512F-NEXT: .cfi_def_cfa_register %ebp
496+
; X86-AVX512F-NEXT: andl $-32, %esp
497+
; X86-AVX512F-NEXT: subl $32, %esp
498+
; X86-AVX512F-NEXT: testb $1, 8(%ebp)
499+
; X86-AVX512F-NEXT: jne .LBB15_2
500+
; X86-AVX512F-NEXT: # %bb.1:
501+
; X86-AVX512F-NEXT: vmovaps 40(%ebp), %ymm1
502+
; X86-AVX512F-NEXT: vmovaps %ymm2, %ymm0
503+
; X86-AVX512F-NEXT: .LBB15_2:
504+
; X86-AVX512F-NEXT: movl %ebp, %esp
505+
; X86-AVX512F-NEXT: popl %ebp
506+
; X86-AVX512F-NEXT: .cfi_def_cfa %esp, 4
507+
; X86-AVX512F-NEXT: retl
508+
;
509+
; X64-AVX512F-LABEL: pr42355_v64i8:
510+
; X64-AVX512F: # %bb.0:
511+
; X64-AVX512F-NEXT: testb $1, %dil
512+
; X64-AVX512F-NEXT: jne .LBB15_2
513+
; X64-AVX512F-NEXT: # %bb.1:
514+
; X64-AVX512F-NEXT: vmovaps %ymm2, %ymm0
515+
; X64-AVX512F-NEXT: vmovaps %ymm3, %ymm1
516+
; X64-AVX512F-NEXT: .LBB15_2:
517+
; X64-AVX512F-NEXT: retq
518+
;
519+
; X86-AVX512BW-LABEL: pr42355_v64i8:
520+
; X86-AVX512BW: # %bb.0:
521+
; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp)
522+
; X86-AVX512BW-NEXT: jne .LBB15_2
523+
; X86-AVX512BW-NEXT: # %bb.1:
524+
; X86-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
525+
; X86-AVX512BW-NEXT: .LBB15_2:
526+
; X86-AVX512BW-NEXT: retl
527+
;
528+
; X64-AVX512BW-LABEL: pr42355_v64i8:
529+
; X64-AVX512BW: # %bb.0:
530+
; X64-AVX512BW-NEXT: testb $1, %dil
531+
; X64-AVX512BW-NEXT: jne .LBB15_2
532+
; X64-AVX512BW-NEXT: # %bb.1:
533+
; X64-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
534+
; X64-AVX512BW-NEXT: .LBB15_2:
535+
; X64-AVX512BW-NEXT: retq
536+
%a = select i1 %c, <64 x i8> %x, <64 x i8> %y
537+
ret <64 x i8> %a
538+
}
539+

0 commit comments

Comments
 (0)