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[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P
Implement XCValu intrinsics for CV32E40P according to the specification. This commit is part of a patch-set to upstream the vendor specific extensions of CV32E40P that need LLVM intrinsics to implement Clang builtins. Contributors: @CharKeaney, @ChunyuLiao, @jeremybennett, @lewis-revill, @NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie.
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‎llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,18 @@ class ScalarCoreVBitManipGprIntrinsic
1818
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
1919
[IntrNoMem, IntrSpeculatable]>;
2020

21+
class ScalarCoreVAluGprIntrinsic
22+
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
23+
[IntrNoMem, IntrSpeculatable]>;
24+
25+
class ScalarCoreVAluGprGprIntrinsic
26+
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
27+
[IntrNoMem, IntrSpeculatable]>;
28+
29+
class ScalarCoreVAluGprGprGprIntrinsic
30+
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
31+
[IntrNoMem, IntrSpeculatable]>;
32+
2133
let TargetPrefix = "riscv" in {
2234
def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
2335
def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
@@ -34,4 +46,15 @@ let TargetPrefix = "riscv" in {
3446
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
3547
[IntrNoMem, IntrWillReturn, IntrSpeculatable,
3648
ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
49+
50+
def int_riscv_cv_alu_clip : ScalarCoreVAluGprGprIntrinsic;
51+
def int_riscv_cv_alu_clipu : ScalarCoreVAluGprGprIntrinsic;
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def int_riscv_cv_alu_addn : ScalarCoreVAluGprGprGprIntrinsic;
53+
def int_riscv_cv_alu_addun : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_addrn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_addurn : ScalarCoreVAluGprGprGprIntrinsic;
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def int_riscv_cv_alu_subn : ScalarCoreVAluGprGprGprIntrinsic;
57+
def int_riscv_cv_alu_subun : ScalarCoreVAluGprGprGprIntrinsic;
58+
def int_riscv_cv_alu_subrn : ScalarCoreVAluGprGprGprIntrinsic;
59+
def int_riscv_cv_alu_suburn : ScalarCoreVAluGprGprGprIntrinsic;
3760
} // TargetPrefix = "riscv"

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -250,10 +250,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
250250
if (RV64LegalI32 && Subtarget.is64Bit())
251251
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
252252

253-
setCondCodeAction(ISD::SETLE, XLenVT, Expand);
253+
if (!Subtarget.hasVendorXCValu())
254+
setCondCodeAction(ISD::SETLE, XLenVT, Expand);
254255
setCondCodeAction(ISD::SETGT, XLenVT, Custom);
255256
setCondCodeAction(ISD::SETGE, XLenVT, Expand);
256-
setCondCodeAction(ISD::SETULE, XLenVT, Expand);
257+
if (!Subtarget.hasVendorXCValu())
258+
setCondCodeAction(ISD::SETULE, XLenVT, Expand);
257259
setCondCodeAction(ISD::SETUGT, XLenVT, Custom);
258260
setCondCodeAction(ISD::SETUGE, XLenVT, Expand);
259261

@@ -1453,6 +1455,16 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
14531455
setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
14541456
}
14551457

1458+
if (Subtarget.hasVendorXCValu()) {
1459+
setOperationAction(ISD::ABS, XLenVT, Legal);
1460+
setOperationAction(ISD::SMIN, XLenVT, Legal);
1461+
setOperationAction(ISD::UMIN, XLenVT, Legal);
1462+
setOperationAction(ISD::SMAX, XLenVT, Legal);
1463+
setOperationAction(ISD::UMAX, XLenVT, Legal);
1464+
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
1465+
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
1466+
}
1467+
14561468
// Function alignments.
14571469
const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
14581470
setMinFunctionAlignment(FunctionAlignment);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 61 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ let DecoderNamespace = "XCValu" in {
198198

199199
} // DecoderNamespace = "XCValu"
200200

201-
let Predicates = [HasVendorXCValu],
201+
let Predicates = [HasVendorXCValu, IsRV32],
202202
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
203203
// General ALU Operations
204204
def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
@@ -249,10 +249,10 @@ let Predicates = [HasVendorXCValu],
249249
Sched<[]>;
250250
def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
251251
Sched<[]>;
252-
} // Predicates = [HasVendorXCValu],
252+
} // Predicates = [HasVendorXCValu, IsRV32],
253253
// hasSideEffects = 0, mayLoad = 0, mayStore = 0
254254

255-
let Predicates = [HasVendorXCValu],
255+
let Predicates = [HasVendorXCValu, IsRV32],
256256
hasSideEffects = 0, mayLoad = 0, mayStore = 0,
257257
Constraints = "$rd = $rd_wb" in {
258258
def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
@@ -272,7 +272,7 @@ let Predicates = [HasVendorXCValu],
272272
def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
273273
Sched<[]>;
274274

275-
} // Predicates = [HasVendorXCValu],
275+
} // Predicates = [HasVendorXCValu, IsRV32],
276276
// hasSideEffects = 0, mayLoad = 0, mayStore = 0,
277277
// Constraints = "$rd = $rd_wb"
278278

@@ -705,6 +705,8 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
705705
def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
706706
def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
707707
def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
708+
def cv_uimm_pow2: Operand<XLenVT>,
709+
ImmLeaf<XLenVT, [{return isPowerOf2_32(Imm + 1);}]>;
708710

709711
def CV_LO5: SDNodeXForm<imm, [{
710712
return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
@@ -716,6 +718,14 @@ def CV_HI5: SDNodeXForm<imm, [{
716718
N->getValueType(0));
717719
}]>;
718720

721+
def powerOf2Minus1 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(Imm+1); }]>;
722+
def negativePowerOf2 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(-Imm); }]>;
723+
def trailing1sPlus1 : SDNodeXForm<imm, [{
724+
return CurDAG->getTargetConstant(
725+
llvm::countr_one(N->getZExtValue()) + 1,
726+
SDLoc(N), N->getValueType(0));
727+
}]>;
728+
719729
multiclass PatCoreVBitManip<Intrinsic intr> {
720730
def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
721731
def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
@@ -748,8 +758,54 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
748758
def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
749759
}
750760

761+
class PatCoreVAluGpr<string intr, string asm> :
762+
PatGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
763+
!cast<RVInst>("CV_" # asm)>;
764+
class PatCoreVAluGprGpr <string intr, string asm> :
765+
PatGprGpr<!cast<Intrinsic>("int_riscv_cv_alu_" # intr),
766+
!cast<RVInst>("CV_" # asm)>;
767+
768+
multiclass PatCoreVAluGprImm<Intrinsic intr> {
769+
def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
770+
def : Pat<(intr (XLenVT GPR:$rs1), powerOf2Minus1:$upperBound),
771+
(!cast<RVInst>("CV_" # NAME) GPR:$rs1,
772+
(trailing1sPlus1 imm:$upperBound))>;
773+
}
774+
775+
multiclass PatCoreVAluGprGprImm<Intrinsic intr> {
776+
def : Pat<(intr GPR:$rs1, GPR:$rs2, GPR:$rs3),
777+
(!cast<RVInst>("CV_" # NAME # "R") GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
778+
def : Pat<(intr GPR:$rs1, GPR:$rs2, uimm5:$imm),
779+
(!cast<RVInst>("CV_" # NAME) GPR:$rs1, GPR:$rs2, uimm5:$imm)>;
780+
}
781+
782+
let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
783+
def : PatGpr<abs, CV_ABS>;
784+
def : PatGprGpr<setle, CV_SLET>;
785+
def : PatGprGpr<setule, CV_SLETU>;
786+
def : PatGprGpr<smin, CV_MIN>;
787+
def : PatGprGpr<umin, CV_MINU>;
788+
def : PatGprGpr<smax, CV_MAX>;
789+
def : PatGprGpr<umax, CV_MAXU>;
790+
791+
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (CV_EXTHS GPR:$rs1)>;
792+
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (CV_EXTBS GPR:$rs1)>;
793+
def : Pat<(and (XLenVT GPR:$rs1), 0xffff), (CV_EXTHZ GPR:$rs1)>;
794+
795+
defm CLIP : PatCoreVAluGprImm<int_riscv_cv_alu_clip>;
796+
defm CLIPU : PatCoreVAluGprImm<int_riscv_cv_alu_clipu>;
797+
defm ADDN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addn>;
798+
defm ADDUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addun>;
799+
defm ADDRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addrn>;
800+
defm ADDURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_addurn>;
801+
defm SUBN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subn>;
802+
defm SUBUN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subun>;
803+
defm SUBRN : PatCoreVAluGprGprImm<int_riscv_cv_alu_subrn>;
804+
defm SUBURN : PatCoreVAluGprGprImm<int_riscv_cv_alu_suburn>;
805+
} // Predicates = [HasVendorXCValu, IsRV32]
806+
751807
//===----------------------------------------------------------------------===//
752-
// Patterns for immediate branching operations
808+
// Patterns for immediate branching operations
753809
//===----------------------------------------------------------------------===//
754810

755811
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {

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