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[LoongArch][NFC] Revise instruction format to match lsx and lasx styles
 Replace lengthy `0b...` binary form with a unified 32-bit hexadecimal representation for opcode. This reduces complexity when dealing with opcode discontinuities.
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5 files changed

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‎llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

Lines changed: 70 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -33,91 +33,91 @@ def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>;
3333
let Predicates = [HasBasicF] in {
3434

3535
// Arithmetic Operation Instructions
36-
def FADD_S : FP_ALU_3R<0b00000001000000001, FPR32>;
37-
def FSUB_S : FP_ALU_3R<0b00000001000000101, FPR32>;
38-
def FMUL_S : FP_ALU_3R<0b00000001000001001, FPR32>;
39-
def FDIV_S : FP_ALU_3R<0b00000001000001101, FPR32>;
40-
def FMADD_S : FP_ALU_4R<0b000010000001, FPR32>;
41-
def FMSUB_S : FP_ALU_4R<0b000010000101, FPR32>;
42-
def FNMADD_S : FP_ALU_4R<0b000010001001, FPR32>;
43-
def FNMSUB_S : FP_ALU_4R<0b000010001101, FPR32>;
44-
def FMAX_S : FP_ALU_3R<0b00000001000010001, FPR32>;
45-
def FMIN_S : FP_ALU_3R<0b00000001000010101, FPR32>;
46-
def FMAXA_S : FP_ALU_3R<0b00000001000011001, FPR32>;
47-
def FMINA_S : FP_ALU_3R<0b00000001000011101, FPR32>;
48-
def FABS_S : FP_ALU_2R<0b0000000100010100000001, FPR32>;
49-
def FNEG_S : FP_ALU_2R<0b0000000100010100000101, FPR32>;
50-
def FSQRT_S : FP_ALU_2R<0b0000000100010100010001, FPR32>;
51-
def FRECIP_S : FP_ALU_2R<0b0000000100010100010101, FPR32>;
52-
def FRSQRT_S : FP_ALU_2R<0b0000000100010100011001, FPR32>;
53-
def FSCALEB_S : FP_ALU_3R<0b00000001000100001, FPR32>;
54-
def FLOGB_S : FP_ALU_2R<0b0000000100010100001001, FPR32>;
55-
def FCOPYSIGN_S : FP_ALU_3R<0b00000001000100101, FPR32>;
56-
def FCLASS_S : FP_ALU_2R<0b0000000100010100001101, FPR32>;
36+
def FADD_S : FP_ALU_3R<0x01008000>;
37+
def FSUB_S : FP_ALU_3R<0x01028000>;
38+
def FMUL_S : FP_ALU_3R<0x01048000>;
39+
def FDIV_S : FP_ALU_3R<0x01068000>;
40+
def FMADD_S : FP_ALU_4R<0x08100000>;
41+
def FMSUB_S : FP_ALU_4R<0x08500000>;
42+
def FNMADD_S : FP_ALU_4R<0x08900000>;
43+
def FNMSUB_S : FP_ALU_4R<0x08d00000>;
44+
def FMAX_S : FP_ALU_3R<0x01088000>;
45+
def FMIN_S : FP_ALU_3R<0x010a8000>;
46+
def FMAXA_S : FP_ALU_3R<0x010c8000>;
47+
def FMINA_S : FP_ALU_3R<0x010e8000>;
48+
def FABS_S : FP_ALU_2R<0x01140400>;
49+
def FNEG_S : FP_ALU_2R<0x01141400>;
50+
def FSQRT_S : FP_ALU_2R<0x01144400>;
51+
def FRECIP_S : FP_ALU_2R<0x01145400>;
52+
def FRSQRT_S : FP_ALU_2R<0x01146400>;
53+
def FSCALEB_S : FP_ALU_3R<0x01108000>;
54+
def FLOGB_S : FP_ALU_2R<0x01142400>;
55+
def FCOPYSIGN_S : FP_ALU_3R<0x01128000>;
56+
def FCLASS_S : FP_ALU_2R<0x01143400>;
5757

5858

5959
// Comparison Instructions
60-
def FCMP_CAF_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CAF, FPR32>;
61-
def FCMP_CUN_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUN, FPR32>;
62-
def FCMP_CEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CEQ, FPR32>;
63-
def FCMP_CUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUEQ, FPR32>;
64-
def FCMP_CLT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLT, FPR32>;
65-
def FCMP_CULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULT, FPR32>;
66-
def FCMP_CLE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLE, FPR32>;
67-
def FCMP_CULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULE, FPR32>;
68-
def FCMP_CNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CNE, FPR32>;
69-
def FCMP_COR_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_COR, FPR32>;
70-
def FCMP_CUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUNE, FPR32>;
71-
def FCMP_SAF_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SAF, FPR32>;
72-
def FCMP_SUN_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUN, FPR32>;
73-
def FCMP_SEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SEQ, FPR32>;
74-
def FCMP_SUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUEQ, FPR32>;
75-
def FCMP_SLT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLT, FPR32>;
76-
def FCMP_SULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULT, FPR32>;
77-
def FCMP_SLE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLE, FPR32>;
78-
def FCMP_SULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULE, FPR32>;
79-
def FCMP_SNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SNE, FPR32>;
80-
def FCMP_SOR_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SOR, FPR32>;
81-
def FCMP_SUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUNE, FPR32>;
60+
def FCMP_CAF_S : FP_CMP<0x0c100000>;
61+
def FCMP_CUN_S : FP_CMP<0x0c140000>;
62+
def FCMP_CEQ_S : FP_CMP<0x0c120000>;
63+
def FCMP_CUEQ_S : FP_CMP<0x0c160000>;
64+
def FCMP_CLT_S : FP_CMP<0x0c110000>;
65+
def FCMP_CULT_S : FP_CMP<0x0c150000>;
66+
def FCMP_CLE_S : FP_CMP<0x0c130000>;
67+
def FCMP_CULE_S : FP_CMP<0x0c170000>;
68+
def FCMP_CNE_S : FP_CMP<0x0c180000>;
69+
def FCMP_COR_S : FP_CMP<0x0c1a0000>;
70+
def FCMP_CUNE_S : FP_CMP<0x0c1c0000>;
71+
def FCMP_SAF_S : FP_CMP<0x0c108000>;
72+
def FCMP_SUN_S : FP_CMP<0x0c148000>;
73+
def FCMP_SEQ_S : FP_CMP<0x0c128000>;
74+
def FCMP_SUEQ_S : FP_CMP<0x0c168000>;
75+
def FCMP_SLT_S : FP_CMP<0x0c118000>;
76+
def FCMP_SULT_S : FP_CMP<0x0c158000>;
77+
def FCMP_SLE_S : FP_CMP<0x0c138000>;
78+
def FCMP_SULE_S : FP_CMP<0x0c178000>;
79+
def FCMP_SNE_S : FP_CMP<0x0c188000>;
80+
def FCMP_SOR_S : FP_CMP<0x0c1a8000>;
81+
def FCMP_SUNE_S : FP_CMP<0x0c1c8000>;
8282

8383
// Conversion Instructions
84-
def FFINT_S_W : FP_CONV<0b0000000100011101000100, FPR32, FPR32>;
85-
def FTINT_W_S : FP_CONV<0b0000000100011011000001, FPR32, FPR32>;
86-
def FTINTRM_W_S : FP_CONV<0b0000000100011010000001, FPR32, FPR32>;
87-
def FTINTRP_W_S : FP_CONV<0b0000000100011010010001, FPR32, FPR32>;
88-
def FTINTRZ_W_S : FP_CONV<0b0000000100011010100001, FPR32, FPR32>;
89-
def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, FPR32, FPR32>;
90-
def FRINT_S : FP_CONV<0b0000000100011110010001, FPR32, FPR32>;
84+
def FFINT_S_W : FP_CONV<0x011d1000>;
85+
def FTINT_W_S : FP_CONV<0x011b0400>;
86+
def FTINTRM_W_S : FP_CONV<0x011a0400>;
87+
def FTINTRP_W_S : FP_CONV<0x011a4400>;
88+
def FTINTRZ_W_S : FP_CONV<0x011a8400>;
89+
def FTINTRNE_W_S : FP_CONV<0x011ac400>;
90+
def FRINT_S : FP_CONV<0x011e4400>;
9191

9292
// Move Instructions
93-
def FSEL_xS : FP_SEL<0b00001101000000, FPR32>;
94-
def FMOV_S : FP_MOV<0b0000000100010100100101, FPR32, FPR32>;
95-
def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, FPR32, GPR>;
96-
def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, GPR, FPR32>;
93+
def FSEL_xS : FP_SEL<0x0d000000>;
94+
def FMOV_S : FP_MOV<0x01149400>;
95+
def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
96+
def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
9797
let hasSideEffects = 1 in {
98-
def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, FCSR, GPR>;
99-
def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, GPR, FCSR>;
98+
def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>;
99+
def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>;
100100
} // hasSideEffects = 1
101-
def MOVFR2CF_xS : FP_MOV<0b0000000100010100110100, CFR, FPR32>;
102-
def MOVCF2FR_xS : FP_MOV<0b0000000100010100110101, FPR32, CFR>;
103-
def MOVGR2CF : FP_MOV<0b0000000100010100110110, CFR, GPR>;
104-
def MOVCF2GR : FP_MOV<0b0000000100010100110111, GPR, CFR>;
101+
def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
102+
def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
103+
def MOVGR2CF : FP_MOV<0x0114d800, CFR, GPR>;
104+
def MOVCF2GR : FP_MOV<0x0114dc00, GPR, CFR>;
105105

106106
// Branch Instructions
107-
def BCEQZ : FP_BRANCH<0b01001000>;
108-
def BCNEZ : FP_BRANCH<0b01001001>;
107+
def BCEQZ : FP_BRANCH<0x48000000>;
108+
def BCNEZ : FP_BRANCH<0x48000100>;
109109

110110
// Common Memory Access Instructions
111-
def FLD_S : FP_LOAD_2RI12<0b0010101100, FPR32>;
112-
def FST_S : FP_STORE_2RI12<0b0010101101, FPR32>;
113-
def FLDX_S : FP_LOAD_3R<0b00111000001100000, FPR32>;
114-
def FSTX_S : FP_STORE_3R<0b00111000001110000, FPR32>;
111+
def FLD_S : FP_LOAD_2RI12<0x2b000000>;
112+
def FST_S : FP_STORE_2RI12<0x2b400000>;
113+
def FLDX_S : FP_LOAD_3R<0x38300000>;
114+
def FSTX_S : FP_STORE_3R<0x38380000>;
115115

116116
// Bound Check Memory Access Instructions
117-
def FLDGT_S : FP_LOAD_3R<0b00111000011101000, FPR32>;
118-
def FLDLE_S : FP_LOAD_3R<0b00111000011101010, FPR32>;
119-
def FSTGT_S : FP_STORE_3R<0b00111000011101100, FPR32>;
120-
def FSTLE_S : FP_STORE_3R<0b00111000011101110, FPR32>;
117+
def FLDGT_S : FP_LOAD_3R<0x38740000>;
118+
def FLDLE_S : FP_LOAD_3R<0x38750000>;
119+
def FSTGT_S : FP_STORE_3R<0x38760000>;
120+
def FSTLE_S : FP_STORE_3R<0x38770000>;
121121

122122
// Pseudo instructions for spill/reload CFRs.
123123
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in

‎llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

Lines changed: 80 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -17,111 +17,111 @@
1717
let Predicates = [HasBasicD] in {
1818

1919
// Arithmetic Operation Instructions
20-
def FADD_D : FP_ALU_3R<0b00000001000000010, FPR64>;
21-
def FSUB_D : FP_ALU_3R<0b00000001000000110, FPR64>;
22-
def FMUL_D : FP_ALU_3R<0b00000001000001010, FPR64>;
23-
def FDIV_D : FP_ALU_3R<0b00000001000001110, FPR64>;
24-
def FMADD_D : FP_ALU_4R<0b000010000010, FPR64>;
25-
def FMSUB_D : FP_ALU_4R<0b000010000110, FPR64>;
26-
def FNMADD_D : FP_ALU_4R<0b000010001010, FPR64>;
27-
def FNMSUB_D : FP_ALU_4R<0b000010001110, FPR64>;
28-
def FMAX_D : FP_ALU_3R<0b00000001000010010, FPR64>;
29-
def FMIN_D : FP_ALU_3R<0b00000001000010110, FPR64>;
30-
def FMAXA_D : FP_ALU_3R<0b00000001000011010, FPR64>;
31-
def FMINA_D : FP_ALU_3R<0b00000001000011110, FPR64>;
32-
def FABS_D : FP_ALU_2R<0b0000000100010100000010, FPR64>;
33-
def FNEG_D : FP_ALU_2R<0b0000000100010100000110, FPR64>;
34-
def FSQRT_D : FP_ALU_2R<0b0000000100010100010010, FPR64>;
35-
def FRECIP_D : FP_ALU_2R<0b0000000100010100010110, FPR64>;
36-
def FRSQRT_D : FP_ALU_2R<0b0000000100010100011010, FPR64>;
37-
def FSCALEB_D : FP_ALU_3R<0b00000001000100010, FPR64>;
38-
def FLOGB_D : FP_ALU_2R<0b0000000100010100001010, FPR64>;
39-
def FCOPYSIGN_D : FP_ALU_3R<0b00000001000100110, FPR64>;
40-
def FCLASS_D : FP_ALU_2R<0b0000000100010100001110, FPR64>;
20+
def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
21+
def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
22+
def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
23+
def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
24+
def FMADD_D : FP_ALU_4R<0x08200000, FPR64>;
25+
def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>;
26+
def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
27+
def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
28+
def FMAX_D : FP_ALU_3R<0x01090000, FPR64>;
29+
def FMIN_D : FP_ALU_3R<0x010b0000, FPR64>;
30+
def FMAXA_D : FP_ALU_3R<0x010d0000, FPR64>;
31+
def FMINA_D : FP_ALU_3R<0x010f0000, FPR64>;
32+
def FABS_D : FP_ALU_2R<0x01140800, FPR64>;
33+
def FNEG_D : FP_ALU_2R<0x01141800, FPR64>;
34+
def FSQRT_D : FP_ALU_2R<0x01144800, FPR64>;
35+
def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>;
36+
def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>;
37+
def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>;
38+
def FLOGB_D : FP_ALU_2R<0x01142800, FPR64>;
39+
def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>;
40+
def FCLASS_D : FP_ALU_2R<0x01143800, FPR64>;
4141

4242
// Comparison Instructions
43-
def FCMP_CAF_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CAF, FPR64>;
44-
def FCMP_CUN_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUN, FPR64>;
45-
def FCMP_CEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CEQ, FPR64>;
46-
def FCMP_CUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUEQ, FPR64>;
47-
def FCMP_CLT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLT, FPR64>;
48-
def FCMP_CULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULT, FPR64>;
49-
def FCMP_CLE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLE, FPR64>;
50-
def FCMP_CULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULE, FPR64>;
51-
def FCMP_CNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CNE, FPR64>;
52-
def FCMP_COR_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_COR, FPR64>;
53-
def FCMP_CUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUNE, FPR64>;
54-
def FCMP_SAF_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SAF, FPR64>;
55-
def FCMP_SUN_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUN, FPR64>;
56-
def FCMP_SEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SEQ, FPR64>;
57-
def FCMP_SUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUEQ, FPR64>;
58-
def FCMP_SLT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLT, FPR64>;
59-
def FCMP_SULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULT, FPR64>;
60-
def FCMP_SLE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLE, FPR64>;
61-
def FCMP_SULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULE, FPR64>;
62-
def FCMP_SNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SNE, FPR64>;
63-
def FCMP_SOR_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SOR, FPR64>;
64-
def FCMP_SUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUNE, FPR64>;
43+
def FCMP_CAF_D : FP_CMP<0x0c200000, FPR64>;
44+
def FCMP_CUN_D : FP_CMP<0x0c240000, FPR64>;
45+
def FCMP_CEQ_D : FP_CMP<0x0c220000, FPR64>;
46+
def FCMP_CUEQ_D : FP_CMP<0x0c260000, FPR64>;
47+
def FCMP_CLT_D : FP_CMP<0x0c210000, FPR64>;
48+
def FCMP_CULT_D : FP_CMP<0x0c250000, FPR64>;
49+
def FCMP_CLE_D : FP_CMP<0x0c230000, FPR64>;
50+
def FCMP_CULE_D : FP_CMP<0x0c270000, FPR64>;
51+
def FCMP_CNE_D : FP_CMP<0x0c280000, FPR64>;
52+
def FCMP_COR_D : FP_CMP<0x0c2a0000, FPR64>;
53+
def FCMP_CUNE_D : FP_CMP<0x0c2c0000, FPR64>;
54+
def FCMP_SAF_D : FP_CMP<0x0c208000, FPR64>;
55+
def FCMP_SUN_D : FP_CMP<0x0c248000, FPR64>;
56+
def FCMP_SEQ_D : FP_CMP<0x0c228000, FPR64>;
57+
def FCMP_SUEQ_D : FP_CMP<0x0c268000, FPR64>;
58+
def FCMP_SLT_D : FP_CMP<0x0c218000, FPR64>;
59+
def FCMP_SULT_D : FP_CMP<0x0c258000, FPR64>;
60+
def FCMP_SLE_D : FP_CMP<0x0c238000, FPR64>;
61+
def FCMP_SULE_D : FP_CMP<0x0c278000, FPR64>;
62+
def FCMP_SNE_D : FP_CMP<0x0c288000, FPR64>;
63+
def FCMP_SOR_D : FP_CMP<0x0c2a8000, FPR64>;
64+
def FCMP_SUNE_D : FP_CMP<0x0c2c8000, FPR64>;
6565

6666
// Conversion Instructions
67-
def FFINT_S_L : FP_CONV<0b0000000100011101000110, FPR32, FPR64>;
68-
def FTINT_L_S : FP_CONV<0b0000000100011011001001, FPR64, FPR32>;
69-
def FTINTRM_L_S : FP_CONV<0b0000000100011010001001, FPR64, FPR32>;
70-
def FTINTRP_L_S : FP_CONV<0b0000000100011010011001, FPR64, FPR32>;
71-
def FTINTRZ_L_S : FP_CONV<0b0000000100011010101001, FPR64, FPR32>;
72-
def FTINTRNE_L_S : FP_CONV<0b0000000100011010111001, FPR64, FPR32>;
73-
def FCVT_S_D : FP_CONV<0b0000000100011001000110, FPR32, FPR64>;
74-
def FCVT_D_S : FP_CONV<0b0000000100011001001001, FPR64, FPR32>;
75-
def FFINT_D_W : FP_CONV<0b0000000100011101001000, FPR64, FPR32>;
76-
def FFINT_D_L : FP_CONV<0b0000000100011101001010, FPR64, FPR64>;
77-
def FTINT_W_D : FP_CONV<0b0000000100011011000010, FPR32, FPR64>;
78-
def FTINT_L_D : FP_CONV<0b0000000100011011001010, FPR64, FPR64>;
79-
def FTINTRM_W_D : FP_CONV<0b0000000100011010000010, FPR32, FPR64>;
80-
def FTINTRM_L_D : FP_CONV<0b0000000100011010001010, FPR64, FPR64>;
81-
def FTINTRP_W_D : FP_CONV<0b0000000100011010010010, FPR32, FPR64>;
82-
def FTINTRP_L_D : FP_CONV<0b0000000100011010011010, FPR64, FPR64>;
83-
def FTINTRZ_W_D : FP_CONV<0b0000000100011010100010, FPR32, FPR64>;
84-
def FTINTRZ_L_D : FP_CONV<0b0000000100011010101010, FPR64, FPR64>;
85-
def FTINTRNE_W_D : FP_CONV<0b0000000100011010110010, FPR32, FPR64>;
86-
def FTINTRNE_L_D : FP_CONV<0b0000000100011010111010, FPR64, FPR64>;
87-
def FRINT_D : FP_CONV<0b0000000100011110010010, FPR64, FPR64>;
67+
def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>;
68+
def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>;
69+
def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>;
70+
def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>;
71+
def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>;
72+
def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>;
73+
def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>;
74+
def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>;
75+
def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>;
76+
def FFINT_D_L : FP_CONV<0x011d2800, FPR64, FPR64>;
77+
def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR64>;
78+
def FTINT_L_D : FP_CONV<0x011b2800, FPR64, FPR64>;
79+
def FTINTRM_W_D : FP_CONV<0x011a0800, FPR32, FPR64>;
80+
def FTINTRM_L_D : FP_CONV<0x011a2800, FPR64, FPR64>;
81+
def FTINTRP_W_D : FP_CONV<0x011a4800, FPR32, FPR64>;
82+
def FTINTRP_L_D : FP_CONV<0x011a6800, FPR64, FPR64>;
83+
def FTINTRZ_W_D : FP_CONV<0x011a8800, FPR32, FPR64>;
84+
def FTINTRZ_L_D : FP_CONV<0x011aa800, FPR64, FPR64>;
85+
def FTINTRNE_W_D : FP_CONV<0x011ac800, FPR32, FPR64>;
86+
def FTINTRNE_L_D : FP_CONV<0x011ae800, FPR64, FPR64>;
87+
def FRINT_D : FP_CONV<0x011e4800, FPR64, FPR64>;
8888

8989
// Move Instructions
90-
def FMOV_D : FP_MOV<0b0000000100010100100110, FPR64, FPR64>;
91-
def MOVFRH2GR_S : FP_MOV<0b0000000100010100101111, GPR, FPR64>;
90+
def FMOV_D : FP_MOV<0x01149800, FPR64, FPR64>;
91+
def MOVFRH2GR_S : FP_MOV<0x0114bc00, GPR, FPR64>;
9292
let isCodeGenOnly = 1 in {
93-
def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, GPR, FPR64>;
94-
def FSEL_xD : FP_SEL<0b00001101000000, FPR64>;
93+
def MOVFR2GR_S_64 : FP_MOV<0x0114b400, GPR, FPR64>;
94+
def FSEL_xD : FP_SEL<0x0d000000, FPR64>;
9595
} // isCodeGenOnly = 1
9696
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in {
97-
def MOVGR2FRH_W : FPFmtMOV<0b0000000100010100101011, (outs FPR64:$out),
97+
def MOVGR2FRH_W : FPFmtMOV<0x0114ac00, (outs FPR64:$out),
9898
(ins FPR64:$dst, GPR:$src),
9999
"$dst, $src">;
100100
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out"
101101

102102
// Common Memory Access Instructions
103-
def FLD_D : FP_LOAD_2RI12<0b0010101110, FPR64>;
104-
def FST_D : FP_STORE_2RI12<0b0010101111, FPR64>;
105-
def FLDX_D : FP_LOAD_3R<0b00111000001101000, FPR64>;
106-
def FSTX_D : FP_STORE_3R<0b00111000001111000, FPR64>;
103+
def FLD_D : FP_LOAD_2RI12<0x2b800000, FPR64>;
104+
def FST_D : FP_STORE_2RI12<0x2bc00000, FPR64>;
105+
def FLDX_D : FP_LOAD_3R<0x38340000, FPR64>;
106+
def FSTX_D : FP_STORE_3R<0x383c0000, FPR64>;
107107

108108
// Bound Check Memory Access Instructions
109-
def FLDGT_D : FP_LOAD_3R<0b00111000011101001, FPR64>;
110-
def FLDLE_D : FP_LOAD_3R<0b00111000011101011, FPR64>;
111-
def FSTGT_D : FP_STORE_3R<0b00111000011101101, FPR64>;
112-
def FSTLE_D : FP_STORE_3R<0b00111000011101111, FPR64>;
109+
def FLDGT_D : FP_LOAD_3R<0x38748000, FPR64>;
110+
def FLDLE_D : FP_LOAD_3R<0x38758000, FPR64>;
111+
def FSTGT_D : FP_STORE_3R<0x38768000, FPR64>;
112+
def FSTLE_D : FP_STORE_3R<0x38778000, FPR64>;
113113

114114
} // Predicates = [HasBasicD]
115115

116116
// Instructions only available on LA64
117117
let Predicates = [HasBasicD, IsLA64] in {
118-
def MOVGR2FR_D : FP_MOV<0b0000000100010100101010, FPR64, GPR>;
119-
def MOVFR2GR_D : FP_MOV<0b0000000100010100101110, GPR, FPR64>;
118+
def MOVGR2FR_D : FP_MOV<0x0114a800, FPR64, GPR>;
119+
def MOVFR2GR_D : FP_MOV<0x0114b800, GPR, FPR64>;
120120
} // Predicates = [HasBasicD, IsLA64]
121121

122122
// Instructions only available on LA32
123123
let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in {
124-
def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, FPR64, GPR>;
124+
def MOVGR2FR_W_64 : FP_MOV<0x0114a400, FPR64, GPR>;
125125
} // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1
126126

127127
//===----------------------------------------------------------------------===//

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