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Tony Varghese
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[NFC] Add testcases for locking down the xxeval instruction support for ternary operators
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‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-and.ll

Lines changed: 188 additions & 0 deletions
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; Test file to verify the emission of Vector selection instructions when ternary operators are used.
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; Function to test ternary(A, xor(B, C), and(B, C)) for <4 x i32>
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; CHECK-LABEL: ternary_A_xor_BC_and_BC_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxlxor vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_xor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %B, %C
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %xor, <4 x i32> %and
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ret <4 x i32> %res
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}
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; Function to test ternary(A, xor(B, C), and(B, C)) for <2 x i64>
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; CHECK-LABEL: ternary_A_xor_BC_and_BC_2x64
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; CHECK: xxlxor vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_xor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <2 x i64> %B, %C
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %xor, <2 x i64> %and
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ret <2 x i64> %res
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}
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; Function to test ternary(A, nor(B, C), and(B, C)) for <4 x i32>
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; CHECK-LABEL: ternary_A_nor_BC_and_BC_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxlnor vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_nor_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%or = or <4 x i32> %B, %C
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%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %and
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ret <4 x i32> %res
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}
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; Function to test ternary(A, nor(B, C), and(B, C)) for <2 x i64>
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; CHECK-LABEL: ternary_A_nor_BC_and_BC_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxlnor vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_nor_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%or = or <2 x i64> %B, %C
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%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %and
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ret <2 x i64> %res
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}
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; Function to test ternary(A, eqv(B, C), and(B, C)) for <4 x i32>
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; CHECK-LABEL: ternary_A_eqv_BC_and_BC_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxleqv vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_eqv_BC_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %B, %C
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%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %and
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ret <4 x i32> %res
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}
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; Function to test ternary(A, eqv(B, C), and(B, C)) for <2 x i64>
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; CHECK-LABEL: ternary_A_eqv_BC_and_BC_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxleqv vs0, v3, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_eqv_BC_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <2 x i64> %B, %C
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%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %and
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ret <2 x i64> %res
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}
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; Function to test ternary(A, not(C), and(B, C)) for <4 x i32>
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; CHECK-LABEL: ternary_A_not_C_and_BC_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxlnor vs0, v4, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_not_C_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
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ret <4 x i32> %res
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}
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; Function to test ternary(A, not(C), and(B, C)) for <2 x i64>
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; CHECK-LABEL: ternary_A_not_C_and_BC_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxlnor vs0, v4, v4
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_not_C_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
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ret <2 x i64> %res
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}
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; Function to test ternary(A, not(B), and(B, C)) for <4 x i32>
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; CHECK-LABEL: ternary_A_not_B_and_BC_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxlnor vs0, v3, v3
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_not_B_and_BC_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%not = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %and
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ret <4 x i32> %res
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}
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; Function to test ternary(A, not(B), and(B, C)) for <2 x i64>
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; CHECK-LABEL: ternary_A_not_B_and_BC_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxlnor vs0, v3, v3
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; CHECK-NEXT: xxland vs1, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, vs1, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_not_B_and_BC_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%not = xor <2 x i64> %B, <i64 -1, i64 -1> ; Vector not operation
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %and
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ret <2 x i64> %res
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}

‎llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll

Lines changed: 169 additions & 0 deletions
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; Function to test ternary(A, and(B, C), B) for <4 x i32>
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; CHECK-LABEL: ternary_A_and_BC_B_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxland vs0, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %B, %C
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%res = select <4 x i1> %A, <4 x i32> %and, <4 x i32> %B
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ret <4 x i32> %res
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}
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; Function to test ternary(A, and(B, C), B) for <2 x i64>
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; CHECK-LABEL: ternary_A_and_BC_B_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxland vs0, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%and = and <2 x i64> %B, %C
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%res = select <2 x i1> %A, <2 x i64> %and, <2 x i64> %B
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ret <2 x i64> %res
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}
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; Function to test ternary(A, nor(B, C), B) for <4 x i32>
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; CHECK-LABEL: ternary_A_nor_BC_B_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxlnor vs0, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%or = or <4 x i32> %B, %C
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%nor = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector NOR operation
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%res = select <4 x i1> %A, <4 x i32> %nor, <4 x i32> %B
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ret <4 x i32> %res
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}
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; Function to test ternary(A, nor(B, C), B) for <2 x i64>
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; CHECK-LABEL: ternary_A_nor_BC_B_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxlnor vs0, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%or = or <2 x i64> %B, %C
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%nor = xor <2 x i64> %or, <i64 -1, i64 -1> ; Vector NOR operation
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%res = select <2 x i1> %A, <2 x i64> %nor, <2 x i64> %B
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ret <2 x i64> %res
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}
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; Function to test ternary(A, eqv(B, C), B) for <4 x i32>
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; CHECK-LABEL: ternary_A_eqv_BC_B_4x32
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; CHECK: xxspltiw v5, 31
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; CHECK-NEXT: xxleqv vs0, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
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; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %B, %C
85+
%eqv = xor <4 x i32> %xor, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector eqv operation
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%res = select <4 x i1> %A, <4 x i32> %eqv, <4 x i32> %B
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ret <4 x i32> %res
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}
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90+
; Function to test ternary(A, eqv(B, C), B) for <2 x i64>
91+
; CHECK-LABEL: ternary_A_eqv_BC_B_2x64
92+
; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxleqv vs0, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
97+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
101+
%xor = xor <2 x i64> %B, %C
102+
%eqv = xor <2 x i64> %xor, <i64 -1, i64 -1> ; Vector eqv operation
103+
%res = select <2 x i1> %A, <2 x i64> %eqv, <2 x i64> %B
104+
ret <2 x i64> %res
105+
}
106+
107+
; Function to test ternary(A, not(C), B) for <4 x i32>
108+
; CHECK-LABEL: ternary_A_not_C_B_4x32
109+
; CHECK: xxspltiw v5, 31
110+
; CHECK-NEXT: xxlnor vs0, v4, v4
111+
; CHECK-NEXT: vslw v2, v2, v5
112+
; CHECK-NEXT: vsraw v2, v2, v5
113+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_not_C_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
116+
entry:
117+
%not = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector not operation
118+
%res = select <4 x i1> %A, <4 x i32> %not, <4 x i32> %B
119+
ret <4 x i32> %res
120+
}
121+
122+
; Function to test ternary(A, not(C), B) for <2 x i64>
123+
; CHECK-LABEL: ternary_A_not_C_B_2x64
124+
; CHECK: xxlxor v5, v5, v5
125+
; CHECK-NEXT: xxlnor vs0, v4, v4
126+
; CHECK-NEXT: xxsplti32dx v5, 1, 63
127+
; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
129+
; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
131+
define dso_local <2 x i64> @ternary_A_not_C_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
132+
entry:
133+
%not = xor <2 x i64> %C, <i64 -1, i64 -1> ; Vector not operation
134+
%res = select <2 x i1> %A, <2 x i64> %not, <2 x i64> %B
135+
ret <2 x i64> %res
136+
}
137+
138+
; Function to test ternary(A, nand(B, C), B) for <4 x i32>
139+
; CHECK-LABEL: ternary_A_nand_BC_B_4x32
140+
; CHECK: xxspltiw v5, 31
141+
; CHECK-NEXT: xxlnand vs0, v3, v4
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; CHECK-NEXT: vslw v2, v2, v5
143+
; CHECK-NEXT: vsraw v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %B, %C
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%nand = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> ; Vector nand operation
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%res = select <4 x i1> %A, <4 x i32> %nand, <4 x i32> %B
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ret <4 x i32> %res
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}
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; Function to test ternary(A, nand(B, C), B) for <2 x i64>
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; CHECK-LABEL: ternary_A_nand_BC_B_2x64
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; CHECK: xxlxor v5, v5, v5
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; CHECK-NEXT: xxlnand vs0, v3, v4
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; CHECK-NEXT: xxsplti32dx v5, 1, 63
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; CHECK-NEXT: vsld v2, v2, v5
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; CHECK-NEXT: vsrad v2, v2, v5
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; CHECK-NEXT: xxsel v2, v3, vs0, v2
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%and = and <2 x i64> %B, %C
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%nand = xor <2 x i64> %and, <i64 -1, i64 -1> ; Vector nand operation
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%res = select <2 x i1> %A, <2 x i64> %nand, <2 x i64> %B
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ret <2 x i64> %res
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}

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