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[GISel][CombinerHelper] Combine and(trunc(x), trunc(y)) -> trunc(and(x, y))
The "match_ands" pattern is also enabled in the AArch64PostLegalizerCombiner.
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6 files changed

+87
-36
lines changed

6 files changed

+87
-36
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -963,6 +963,9 @@ class CombinerHelper {
963963

964964
// Simplify (cmp cc0 x, y) (&& or ||) (cmp cc1 x, y) -> cmp cc2 x, y.
965965
bool tryFoldLogicOfFCmps(GLogicalBinOp *Logic, BuildFnTy &MatchInfo);
966+
967+
// Simplify (trunc v1) && (trunc v2) -> trunc (v1 && v2)
968+
bool tryFoldAndOfTruncs(GLogicalBinOp *Logical, BuildFnTy &MatchInfo);
966969
};
967970
} // namespace llvm
968971

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6982,9 +6982,69 @@ bool CombinerHelper::tryFoldLogicOfFCmps(GLogicalBinOp *Logic,
69826982
return false;
69836983
}
69846984

6985+
bool CombinerHelper::tryFoldAndOfTruncs(GLogicalBinOp *Logical,
6986+
BuildFnTy &MatchInfo) {
6987+
assert(Logical->getOpcode() == TargetOpcode::G_AND &&
6988+
"Expected to be called with G_AND!");
6989+
Register Dst = Logical->getOperand(0).getReg();
6990+
Register V1 = Logical->getOperand(1).getReg();
6991+
Register V2 = Logical->getOperand(2).getReg();
6992+
6993+
MachineInstr *V1MI = MRI.getUniqueVRegDef(V1);
6994+
MachineInstr *V2MI = MRI.getUniqueVRegDef(V2);
6995+
if (!V1MI || !V2MI)
6996+
return false;
6997+
6998+
bool V1Freeze = V1MI->getOpcode() == TargetOpcode::G_FREEZE;
6999+
bool V2Freeze = V2MI->getOpcode() == TargetOpcode::G_FREEZE;
7000+
if (V1Freeze)
7001+
V1 = V1MI->getOperand(1).getReg();
7002+
if (V2Freeze)
7003+
V2 = V2MI->getOperand(1).getReg();
7004+
7005+
Register V1Src, V2Src;
7006+
if (!mi_match(V1, MRI, m_GTrunc(m_Reg(V1Src))) ||
7007+
!mi_match(V2, MRI, m_GTrunc(m_Reg(V2Src))))
7008+
return false;
7009+
if (!MRI.hasOneNonDBGUse(V1) || !MRI.hasOneNonDBGUse(V2))
7010+
return false;
7011+
7012+
LLT V1Ty = MRI.getType(V1);
7013+
LLT V2Ty = MRI.getType(V2);
7014+
LLT V1SrcTy = MRI.getType(V1Src);
7015+
LLT V2SrcTy = MRI.getType(V2Src);
7016+
7017+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, {V1SrcTy, V2SrcTy}}))
7018+
return false;
7019+
7020+
if (V1Ty != V2Ty || V1SrcTy != V2SrcTy)
7021+
return false;
7022+
7023+
MatchInfo = [=](MachineIRBuilder &B) {
7024+
Register Op0 = V1Src;
7025+
Register Op1 = V2Src;
7026+
7027+
if (V1Freeze)
7028+
Op0 = B.buildFreeze(V1SrcTy, V1Src).getReg(0);
7029+
if (V2Freeze)
7030+
Op1 = B.buildFreeze(V1SrcTy, V2Src).getReg(0);
7031+
7032+
auto And = B.buildAnd(V1SrcTy, Op0, Op1);
7033+
B.buildTrunc(Dst, And);
7034+
7035+
MRI.getUniqueVRegDef(V1)->eraseFromParent();
7036+
MRI.getUniqueVRegDef(V2)->eraseFromParent();
7037+
};
7038+
7039+
return true;
7040+
}
7041+
69857042
bool CombinerHelper::matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) {
69867043
GAnd *And = cast<GAnd>(&MI);
69877044

7045+
if (tryFoldAndOfTruncs(And, MatchInfo))
7046+
return true;
7047+
69887048
if (tryFoldAndOrOrICmpsUsingRanges(And, MatchInfo))
69897049
return true;
69907050

‎llvm/lib/Target/AArch64/AArch64Combine.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -295,5 +295,5 @@ def AArch64PostLegalizerCombiner
295295
ptr_add_immed_chain, overlapping_and,
296296
split_store_zero_128, undef_combines,
297297
select_to_minmax, or_to_bsp, combine_concat_vector,
298-
commute_constant_to_rhs]> {
298+
commute_constant_to_rhs, match_ands]> {
299299
}

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-and-trunc.mir

Lines changed: 12 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,8 @@ body: |
1111
; CHECK-NEXT: {{ $}}
1212
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
1313
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
14-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
15-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
16-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
17-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
18-
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
14+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
15+
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
1916
%0:_(s32) = COPY $w0
2017
%1:_(s32) = COPY $w1
2118
%2:_(s16) = G_TRUNC %0
@@ -88,10 +85,9 @@ body: |
8885
; CHECK-NEXT: {{ $}}
8986
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
9087
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
91-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
92-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY1]](<4 x s32>)
93-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[TRUNC]], [[TRUNC1]]
94-
; CHECK-NEXT: $x0 = COPY [[AND]](<4 x s16>)
88+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY]], [[COPY1]]
89+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[AND]](<4 x s32>)
90+
; CHECK-NEXT: $x0 = COPY [[TRUNC]](<4 x s16>)
9591
%0:_(<4 x s32>) = COPY $q0
9692
%1:_(<4 x s32>) = COPY $q1
9793
%2:_(<4 x s16>) = G_TRUNC %0
@@ -134,12 +130,9 @@ body: |
134130
; CHECK-NEXT: {{ $}}
135131
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
136132
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
137-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
138-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
139-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
140-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[FREEZE]], [[TRUNC1]]
141-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
142-
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
133+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
134+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FREEZE]], [[COPY1]]
135+
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
143136
%0:_(s32) = COPY $w0
144137
%1:_(s32) = COPY $w1
145138
%2:_(s16) = G_TRUNC %0
@@ -159,13 +152,10 @@ body: |
159152
; CHECK-NEXT: {{ $}}
160153
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
161154
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
162-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
163-
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
164-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
165-
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
166-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[FREEZE]], [[FREEZE1]]
167-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
168-
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
155+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
156+
; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
157+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FREEZE]], [[FREEZE1]]
158+
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
169159
%0:_(s32) = COPY $w0
170160
%1:_(s32) = COPY $w1
171161
%2:_(s16) = G_TRUNC %0

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown- --aarch64postlegalizercombiner-only-enable-rule="select_to_logical" %s -o - | FileCheck %s
2+
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
33
# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
44
# REQUIRES: asserts
5+
56
---
67
# select (c, x, x) -> x
78
name: test_combine_select_same_res
@@ -200,10 +201,9 @@ body: |
200201
; CHECK-NEXT: {{ $}}
201202
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
202203
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
203-
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
204-
; CHECK-NEXT: %t:_(s1) = G_TRUNC [[COPY1]](s64)
205-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %t
206-
; CHECK-NEXT: %sel:_(s1) = G_AND %c, [[FREEZE]]
204+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
205+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[FREEZE]]
206+
; CHECK-NEXT: %sel:_(s1) = G_TRUNC [[AND]](s64)
207207
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
208208
; CHECK-NEXT: $w0 = COPY %ext(s32)
209209
%0:_(s64) = COPY $x0
@@ -228,10 +228,9 @@ body: |
228228
; CHECK-NEXT: {{ $}}
229229
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
230230
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
231-
; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64)
232-
; CHECK-NEXT: %t:_(s1) = G_TRUNC [[COPY1]](s64)
233-
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE %t
234-
; CHECK-NEXT: %sel:_(s1) = G_AND %c, [[FREEZE]]
231+
; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
232+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[FREEZE]]
233+
; CHECK-NEXT: %sel:_(s1) = G_TRUNC [[AND]](s64)
235234
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s1)
236235
; CHECK-NEXT: $w0 = COPY %ext(s32)
237236
%0:_(s64) = COPY $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-narrow-binop-feeding-add.mir

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,9 @@ body: |
8484
; CHECK: liveins: $x0, $x1
8585
; CHECK: %binop_lhs:_(s64) = COPY $x0
8686
; CHECK: %binop_rhs:_(s64) = COPY $x1
87-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop_lhs(s64)
88-
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC %binop_rhs(s64)
89-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
90-
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32)
87+
; CHECK: %binop:_(s64) = G_AND %binop_lhs, %binop_rhs
88+
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC %binop(s64)
89+
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s32)
9190
; CHECK: $x0 = COPY [[ZEXT]](s64)
9291
; CHECK: RET_ReallyLR implicit $x0
9392
%binop_lhs:_(s64) = COPY $x0

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