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djtodorodjtodoro
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fixup: Move inst formats to mips td file
1 parent 200f8bb commit 46f8195

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+75
-75
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2 files changed

+75
-75
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 0 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -514,80 +514,6 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
514514
let Inst{6-0} = opcode.Value;
515515
}
516516

517-
//===----------------------------------------------------------------------===//
518-
// MIPS custom instruction formats
519-
//===----------------------------------------------------------------------===//
520-
521-
// Load double pair format.
522-
class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
523-
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
524-
bits<7> imm7;
525-
bits<5> rs1;
526-
bits<5> rd1;
527-
bits<5> rd2;
528-
529-
let Inst{31-27} = rd2;
530-
let Inst{26-23} = imm7{6-3};
531-
let Inst{22-20} = 0b000;
532-
let Inst{19-15} = rs1;
533-
let Inst{14-12} = 0b100;
534-
let Inst{11-7} = rd1;
535-
let Inst{6-0} = OPC_CUSTOM_0.Value;
536-
}
537-
538-
// Load word pair format.
539-
class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
540-
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
541-
bits<7> imm7;
542-
bits<5> rs1;
543-
bits<5> rd1;
544-
bits<5> rd2;
545-
546-
let Inst{31-27} = rd2;
547-
let Inst{26-22} = imm7{6-2};
548-
let Inst{21-20} = 0b01;
549-
let Inst{19-15} = rs1;
550-
let Inst{14-12} = 0b100;
551-
let Inst{11-7} = rd1;
552-
let Inst{6-0} = OPC_CUSTOM_0.Value;
553-
}
554-
555-
// Store double pair format.
556-
class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
557-
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
558-
bits<7> imm7;
559-
bits<5> rs3;
560-
bits<5> rs2;
561-
bits<5> rs1;
562-
563-
let Inst{31-27} = rs3;
564-
let Inst{26-25} = imm7{6-5};
565-
let Inst{24-20} = rs2;
566-
let Inst{19-15} = rs1;
567-
let Inst{14-12} = 0b101;
568-
let Inst{11-10} = imm7{4-3};
569-
let Inst{9-7} = 0b000;
570-
let Inst{6-0} = OPC_CUSTOM_0.Value;
571-
}
572-
573-
// Store word pair format.
574-
class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
575-
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
576-
bits<7> imm7;
577-
bits<5> rs3;
578-
bits<5> rs2;
579-
bits<5> rs1;
580-
581-
let Inst{31-27} = rs3;
582-
let Inst{26-25} = imm7{6-5};
583-
let Inst{24-20} = rs2;
584-
let Inst{19-15} = rs1;
585-
let Inst{14-12} = 0b101;
586-
let Inst{11-9} = imm7{4-2};
587-
let Inst{8-7} = 0b01;
588-
let Inst{6-0} = OPC_CUSTOM_0.Value;
589-
}
590-
591517
//===----------------------------------------------------------------------===//
592518
// Instruction classes for .insn directives
593519
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 75 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,14 +29,88 @@ def uimm7_lsb000 : RISCVOp,
2929
}];
3030
}
3131

32+
//===----------------------------------------------------------------------===//
33+
// MIPS custom instruction formats
34+
//===----------------------------------------------------------------------===//
35+
36+
// Load double pair format.
37+
class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
38+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
39+
bits<7> imm7;
40+
bits<5> rs1;
41+
bits<5> rd1;
42+
bits<5> rd2;
43+
44+
let Inst{31-27} = rd2;
45+
let Inst{26-23} = imm7{6-3};
46+
let Inst{22-20} = 0b000;
47+
let Inst{19-15} = rs1;
48+
let Inst{14-12} = 0b100;
49+
let Inst{11-7} = rd1;
50+
let Inst{6-0} = OPC_CUSTOM_0.Value;
51+
}
52+
53+
// Load word pair format.
54+
class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
55+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
56+
bits<7> imm7;
57+
bits<5> rs1;
58+
bits<5> rd1;
59+
bits<5> rd2;
60+
61+
let Inst{31-27} = rd2;
62+
let Inst{26-22} = imm7{6-2};
63+
let Inst{21-20} = 0b01;
64+
let Inst{19-15} = rs1;
65+
let Inst{14-12} = 0b100;
66+
let Inst{11-7} = rd1;
67+
let Inst{6-0} = OPC_CUSTOM_0.Value;
68+
}
69+
70+
// Store double pair format.
71+
class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
72+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
73+
bits<7> imm7;
74+
bits<5> rs3;
75+
bits<5> rs2;
76+
bits<5> rs1;
77+
78+
let Inst{31-27} = rs3;
79+
let Inst{26-25} = imm7{6-5};
80+
let Inst{24-20} = rs2;
81+
let Inst{19-15} = rs1;
82+
let Inst{14-12} = 0b101;
83+
let Inst{11-10} = imm7{4-3};
84+
let Inst{9-7} = 0b000;
85+
let Inst{6-0} = OPC_CUSTOM_0.Value;
86+
}
87+
88+
// Store word pair format.
89+
class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
90+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
91+
bits<7> imm7;
92+
bits<5> rs3;
93+
bits<5> rs2;
94+
bits<5> rs1;
95+
96+
let Inst{31-27} = rs3;
97+
let Inst{26-25} = imm7{6-5};
98+
let Inst{24-20} = rs2;
99+
let Inst{19-15} = rs1;
100+
let Inst{14-12} = 0b101;
101+
let Inst{11-9} = imm7{4-2};
102+
let Inst{8-7} = 0b01;
103+
let Inst{6-0} = OPC_CUSTOM_0.Value;
104+
}
105+
32106
//===----------------------------------------------------------------------===//
33107
// MIPS extensions
34108
//===----------------------------------------------------------------------===//
35109

36110
let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
37111
DecoderNamespace = "Xmipscmove" in {
38112
def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
39-
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
113+
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
40114
"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
41115
Sched<[]>;
42116
}

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