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[FMV][AArch64] Remove features predres and ls64. (#124266)
These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: ARM-software/acle#382
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14 files changed

+60
-91
lines changed

14 files changed

+60
-91
lines changed

‎clang/test/CodeGen/AArch64/cpu-supports-target.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,8 @@
9191
// CHECK-NEXT: br label %[[RETURN]]
9292
// CHECK: [[IF_ELSE16]]:
9393
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
94-
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 10836786603360256
95-
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 10836786603360256
94+
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 1688849860263936
95+
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 1688849860263936
9696
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
9797
// CHECK-NEXT: br i1 [[TMP39]], label %[[IF_THEN17:.*]], label %[[IF_ELSE18:.*]]
9898
// CHECK: [[IF_THEN17]]:
@@ -142,7 +142,7 @@ int check_all_features() {
142142
return 8;
143143
else if (__builtin_cpu_supports("sme+memtag+sb"))
144144
return 9;
145-
else if (__builtin_cpu_supports("predres+ssbs+bti+ls64"))
145+
else if (__builtin_cpu_supports("ssbs+bti"))
146146
return 10;
147147
else if (__builtin_cpu_supports("wfxt+sme-f64f64"))
148148
return 11;

‎clang/test/CodeGen/AArch64/cpu-supports.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@
2727
// CHECK-NEXT: br label [[RETURN]]
2828
// CHECK: if.end2:
2929
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
30-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 171141184020873984
31-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 171141184020873984
30+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 162133984766132992
31+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 162133984766132992
3232
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
3333
// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
3434
// CHECK: if.then3:
@@ -53,7 +53,7 @@ int main(void) {
5353
if (__builtin_cpu_supports("sve2-aes+memtag"))
5454
return 2;
5555

56-
if (__builtin_cpu_supports("sme2+ls64+wfxt"))
56+
if (__builtin_cpu_supports("sme2+wfxt"))
5757
return 3;
5858

5959
if (__builtin_cpu_supports("avx2"))

‎clang/test/CodeGen/AArch64/fmv-dependencies.c

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -60,9 +60,6 @@ __attribute__((target_version("i8mm"))) int fmv(void) { return 0; }
6060
// CHECK: define dso_local i32 @fmv._Mjscvt() #[[jscvt:[0-9]+]] {
6161
__attribute__((target_version("jscvt"))) int fmv(void) { return 0; }
6262

63-
// CHECK: define dso_local i32 @fmv._Mls64() #[[ls64:[0-9]+]] {
64-
__attribute__((target_version("ls64"))) int fmv(void) { return 0; }
65-
6663
// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
6764
__attribute__((target_version("lse"))) int fmv(void) { return 0; }
6865

@@ -72,9 +69,6 @@ __attribute__((target_version("memtag"))) int fmv(void) { return 0; }
7269
// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
7370
__attribute__((target_version("mops"))) int fmv(void) { return 0; }
7471

75-
// CHECK: define dso_local i32 @fmv._Mpredres() #[[predres:[0-9]+]] {
76-
__attribute__((target_version("predres"))) int fmv(void) { return 0; }
77-
7872
// CHECK: define dso_local i32 @fmv._Mrcpc() #[[rcpc:[0-9]+]] {
7973
__attribute__((target_version("rcpc"))) int fmv(void) { return 0; }
8074

@@ -169,11 +163,9 @@ int caller() {
169163
// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
170164
// CHECK: attributes #[[i8mm]] = { {{.*}} "target-features"="+fp-armv8,+i8mm,+neon,+outline-atomics,+v8a"
171165
// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
172-
// CHECK: attributes #[[ls64]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
173166
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
174167
// CHECK: attributes #[[memtag]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
175168
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
176-
// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
177169
// CHECK: attributes #[[rcpc]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a"
178170
// CHECK: attributes #[[rcpc2]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc-immo,+v8a"
179171
// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc-immo,+rcpc3,+v8a"

‎clang/test/CodeGen/AArch64/fmv-features.c

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -58,9 +58,6 @@ __attribute__((target_version("i8mm"))) int fmv(void) { return 0; }
5858
// CHECK: define dso_local i32 @fmv._Mjscvt() #[[jscvt:[0-9]+]] {
5959
__attribute__((target_version("jscvt"))) int fmv(void) { return 0; }
6060

61-
// CHECK: define dso_local i32 @fmv._Mls64() #[[ls64:[0-9]+]] {
62-
__attribute__((target_version("ls64"))) int fmv(void) { return 0; }
63-
6461
// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
6562
__attribute__((target_version("lse"))) int fmv(void) { return 0; }
6663

@@ -70,9 +67,6 @@ __attribute__((target_version("memtag"))) int fmv(void) { return 0; }
7067
// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
7168
__attribute__((target_version("mops"))) int fmv(void) { return 0; }
7269

73-
// CHECK: define dso_local i32 @fmv._Mpredres() #[[predres:[0-9]+]] {
74-
__attribute__((target_version("predres"))) int fmv(void) { return 0; }
75-
7670
// CHECK: define dso_local i32 @fmv._Mrcpc() #[[rcpc:[0-9]+]] {
7771
__attribute__((target_version("rcpc"))) int fmv(void) { return 0; }
7872

@@ -171,11 +165,9 @@ int caller() {
171165
// CHECK: attributes #[[frintts]] = {{.*}} "fmv-features"="frintts"
172166
// CHECK: attributes #[[i8mm]] = {{.*}} "fmv-features"="i8mm"
173167
// CHECK: attributes #[[jscvt]] = {{.*}} "fmv-features"="jscvt"
174-
// CHECK: attributes #[[ls64]] = {{.*}} "fmv-features"="ls64"
175168
// CHECK: attributes #[[lse]] = {{.*}} "fmv-features"="lse"
176169
// CHECK: attributes #[[memtag]] = {{.*}} "fmv-features"="memtag"
177170
// CHECK: attributes #[[mops]] = {{.*}} "fmv-features"="mops"
178-
// CHECK: attributes #[[predres]] = {{.*}} "fmv-features"="predres"
179171
// CHECK: attributes #[[rcpc]] = {{.*}} "fmv-features"="rcpc"
180172
// CHECK: attributes #[[rcpc2]] = {{.*}} "fmv-features"="rcpc2"
181173
// CHECK: attributes #[[rcpc3]] = {{.*}} "fmv-features"="rcpc3"

‎clang/test/CodeGen/AArch64/fmv-priority.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,15 @@
55
//
66
// MSB LSB
77
//
8-
// sme2 | ls64 | sme | bf16 | | | fp16 | simd | fp
8+
// sme2 | wfxt | sme | bf16 | | | fp16 | simd | fp
99
// -----+------+-----+------+-------+------+------+------+---
1010
// sme2 | | sme | bf16 | rcpc2 | rcpc | fp16 | simd | fp
1111
//
1212
// Dependencies should not affect priorities, since a
1313
// feature can only depend on lower priority features:
1414
// https://github.com/ARM-software/acle/pull/376
1515

16-
__attribute__((target_version("sme2+ls64"))) int fn(void);
16+
__attribute__((target_version("sme2+wfxt"))) int fn(void);
1717
__attribute__((target_version("sme2+rcpc2"))) int fn(void);
1818
__attribute__((target_version("default"))) int fn(void) { return 0; }
1919

@@ -36,12 +36,12 @@ int call() { return fn(); }
3636
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
3737
// CHECK-NEXT: call void @__init_cpu_features_resolver()
3838
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
39-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 153126785511392000
40-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 153126785511392000
39+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 162133984766132992
40+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 162133984766132992
4141
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
4242
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
4343
// CHECK: [[RESOLVER_RETURN]]:
44-
// CHECK-NEXT: ret ptr @fn._Mls64Msme2
44+
// CHECK-NEXT: ret ptr @fn._Msme2Mwfxt
4545
// CHECK: [[RESOLVER_ELSE]]:
4646
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
4747
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 144119586269233920

‎clang/test/CodeGen/attr-target-clones-aarch64.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ int foo() {
1212
return ftc() + ftc_def() + ftc_dup1() + ftc_dup2() + ftc_dup3();
1313
}
1414

15-
inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
15+
inline int __attribute__((target_clones("rng+simd", "rcpc", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
1616
inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void);
1717
inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; }
1818

@@ -336,7 +336,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
336336
//
337337
//
338338
// CHECK: Function Attrs: noinline nounwind optnone
339-
// CHECK-LABEL: define {{[^@]+}}@ftc_inline1._MpredresMrcpc
339+
// CHECK-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc
340340
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
341341
// CHECK-NEXT: entry:
342342
// CHECK-NEXT: ret i32 1
@@ -368,12 +368,12 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
368368
// CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt
369369
// CHECK: resolver_else:
370370
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
371-
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
372-
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
371+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304
372+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304
373373
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
374374
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
375375
// CHECK: resolver_return1:
376-
// CHECK-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
376+
// CHECK-NEXT: ret ptr @ftc_inline1._Mrcpc
377377
// CHECK: resolver_else2:
378378
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
379379
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769
@@ -793,7 +793,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
793793
//
794794
//
795795
// CHECK-MTE-BTI: Function Attrs: noinline nounwind optnone
796-
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._MpredresMrcpc
796+
// CHECK-MTE-BTI-LABEL: define {{[^@]+}}@ftc_inline1._Mrcpc
797797
// CHECK-MTE-BTI-SAME: () #[[ATTR13:[0-9]+]] {
798798
// CHECK-MTE-BTI-NEXT: entry:
799799
// CHECK-MTE-BTI-NEXT: ret i32 1
@@ -825,12 +825,12 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
825825
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt
826826
// CHECK-MTE-BTI: resolver_else:
827827
// CHECK-MTE-BTI-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
828-
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
829-
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
828+
// CHECK-MTE-BTI-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4194304
829+
// CHECK-MTE-BTI-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4194304
830830
// CHECK-MTE-BTI-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
831831
// CHECK-MTE-BTI-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
832832
// CHECK-MTE-BTI: resolver_return1:
833-
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
833+
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline1._Mrcpc
834834
// CHECK-MTE-BTI: resolver_else2:
835835
// CHECK-MTE-BTI-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
836836
// CHECK-MTE-BTI-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 769

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,14 @@
55
int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; }
66
int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; }
77
int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; }
8-
int __attribute__((target_version("dotprod+ls64"))) fmv(void) { return 4; }
8+
int __attribute__((target_version("dotprod+wfxt"))) fmv(void) { return 4; }
99
int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; }
1010
int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; }
11-
int __attribute__((target_version("crc+ls64"))) fmv(void) { return 7; }
11+
int __attribute__((target_version("crc+wfxt"))) fmv(void) { return 7; }
1212
int __attribute__((target_version("bti"))) fmv(void) { return 8; }
1313
int __attribute__((target_version("sme2"))) fmv(void) { return 9; }
1414
int __attribute__((target_version("default"))) fmv(void) { return 0; }
15-
int __attribute__((target_version("ls64+simd"))) fmv_one(void) { return 1; }
15+
int __attribute__((target_version("wfxt+simd"))) fmv_one(void) { return 1; }
1616
int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
1717
int __attribute__((target_version("default"))) fmv_one(void) { return 0; }
1818
int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
@@ -41,7 +41,7 @@ inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 1
4141
inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; }
4242
inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; }
4343

44-
__attribute__((target_version("ls64"))) int fmv_e(void);
44+
__attribute__((target_version("wfxt"))) int fmv_e(void);
4545
int fmv_e(void) { return 20; }
4646

4747
static __attribute__((target_version("sb"))) inline int fmv_d(void);
@@ -173,7 +173,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
173173
//
174174
//
175175
// CHECK: Function Attrs: noinline nounwind optnone
176-
// CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMls64
176+
// CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMwfxt
177177
// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
178178
// CHECK-NEXT: entry:
179179
// CHECK-NEXT: ret i32 4
@@ -194,7 +194,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
194194
//
195195
//
196196
// CHECK: Function Attrs: noinline nounwind optnone
197-
// CHECK-LABEL: define {{[^@]+}}@fmv._McrcMls64
197+
// CHECK-LABEL: define {{[^@]+}}@fmv._McrcMwfxt
198198
// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
199199
// CHECK-NEXT: entry:
200200
// CHECK-NEXT: ret i32 7
@@ -222,7 +222,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
222222
//
223223
//
224224
// CHECK: Function Attrs: noinline nounwind optnone
225-
// CHECK-LABEL: define {{[^@]+}}@fmv_one._Mls64Msimd
225+
// CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMwfxt
226226
// CHECK-SAME: () #[[ATTR10:[0-9]+]] {
227227
// CHECK-NEXT: entry:
228228
// CHECK-NEXT: ret i32 1
@@ -479,20 +479,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
479479
// CHECK-NEXT: ret ptr @fmv._Mflagm2Msme-i16i64
480480
// CHECK: resolver_else2:
481481
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
482-
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 9007199254742016
483-
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 9007199254742016
482+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 18014398509483008
483+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 18014398509483008
484484
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
485485
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
486486
// CHECK: resolver_return3:
487-
// CHECK-NEXT: ret ptr @fmv._McrcMls64
487+
// CHECK-NEXT: ret ptr @fmv._McrcMwfxt
488488
// CHECK: resolver_else4:
489489
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
490-
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 9007199254741776
491-
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 9007199254741776
490+
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 18014398509482768
491+
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 18014398509482768
492492
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
493493
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
494494
// CHECK: resolver_return5:
495-
// CHECK-NEXT: ret ptr @fmv._MdotprodMls64
495+
// CHECK-NEXT: ret ptr @fmv._MdotprodMwfxt
496496
// CHECK: resolver_else6:
497497
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
498498
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624
@@ -541,12 +541,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
541541
// CHECK-NEXT: resolver_entry:
542542
// CHECK-NEXT: call void @__init_cpu_features_resolver()
543543
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
544-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254741760
545-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254741760
544+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509482752
545+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509482752
546546
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
547547
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
548548
// CHECK: resolver_return:
549-
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
549+
// CHECK-NEXT: ret ptr @fmv_one._MsimdMwfxt
550550
// CHECK: resolver_else:
551551
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
552552
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 262144
@@ -593,12 +593,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
593593
// CHECK-NEXT: resolver_entry:
594594
// CHECK-NEXT: call void @__init_cpu_features_resolver()
595595
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
596-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254740992
597-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254740992
596+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509481984
597+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509481984
598598
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
599599
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
600600
// CHECK: resolver_return:
601-
// CHECK-NEXT: ret ptr @fmv_e._Mls64
601+
// CHECK-NEXT: ret ptr @fmv_e._Mwfxt
602602
// CHECK: resolver_else:
603603
// CHECK-NEXT: ret ptr @fmv_e.default
604604
//

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