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[SelectionDAG] Fold (icmp eq/ne (shift X, C), 0) -> (icmp eq/ne X, 0)
Optimize (icmp eq/ne (shift X, C), 0) -> (icmp eq/ne X, 0) We do this if all shifted out bits, as well as shifted in bits, are known to be zero. And we also do it if all shifted out bits are known to be equal to at least one bit that isn't shifted out. Defensively limit this to one-use shifts (haven't really considered if this can be profitable also when there are multiple uses of the shift, but that is likely to depend on the target).
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7 files changed

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7 files changed

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‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4516,6 +4516,27 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
45164516
}
45174517
}
45184518
}
4519+
4520+
// Optimize
4521+
// (icmp eq/ne (shift N00, N01C), 0) -> (icmp eq/ne N00, 0)
4522+
// If shift is logical and all shifted out bits are known to be zero, then
4523+
// the zero'd ness doesnt change and we can omit the shift.
4524+
// If all shifted out bits are equal to at least one bit that isn't
4525+
// shifted out, then the zero'd ness doesnt change and we can omit the
4526+
// shift.
4527+
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1.isZero() &&
4528+
N0.hasOneUse() &&
4529+
(N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL)) {
4530+
if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) {
4531+
SDValue N00 = N0.getOperand(0);
4532+
KnownBits Known = DAG.computeKnownBits(N00);
4533+
if (N0.getOpcode() == ISD::SRL)
4534+
Known = Known.reverseBits();
4535+
if (ShAmt->getAPIntValue().ule(Known.countMinLeadingZeros()) ||
4536+
ShAmt->getAPIntValue().ult(Known.countMinSignBits()))
4537+
return DAG.getSetCC(dl, VT, N00, N1, Cond);
4538+
}
4539+
}
45194540
}
45204541

45214542
// FIXME: Support vectors.

‎llvm/test/CodeGen/ARM/and-cmpz.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -89,12 +89,12 @@ false:
8989
}
9090

9191
; CHECK-LABEL: i16_cmpz:
92-
; T1: uxth r0, r0
93-
; T1-NEXT: lsrs r0, r0, #9
92+
; T1: lsls r0, r0, #16
93+
; T1-NEXT: lsrs r0, r0, #25
9494
; T1-NEXT: bne
95-
; T2: uxth r0, r0
96-
; T2-NEXT: movs r2, #0
97-
; T2-NEXT: cmp.w r2, r0, lsr #9
95+
; T2: tst.w r0, #65024
96+
; T2-NEXT: it
97+
; T2-NEXT: bxne
9898
define void @i16_cmpz(i16 %x, ptr %foo) {
9999
entry:
100100
%cmp = icmp ult i16 %x, 512

‎llvm/test/CodeGen/ARM/simplifysetcc_narrow_load.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -311,7 +311,7 @@ define i1 @test_48_16_8(ptr %y) {
311311
; CHECK-LE-LABEL: test_48_16_8:
312312
; CHECK-LE: @ %bb.0:
313313
; CHECK-LE-NEXT: ldrh r0, [r0, #1]
314-
; CHECK-LE-NEXT: lsls r0, r0, #8
314+
; CHECK-LE-NEXT: cmp r0, #0
315315
; CHECK-LE-NEXT: movne r0, #1
316316
; CHECK-LE-NEXT: mov pc, lr
317317
;
@@ -559,28 +559,28 @@ define i1 @test_24_8_8(ptr %y) {
559559
; CHECK-LE-LABEL: test_24_8_8:
560560
; CHECK-LE: @ %bb.0:
561561
; CHECK-LE-NEXT: ldrb r0, [r0, #1]
562-
; CHECK-LE-NEXT: lsls r0, r0, #8
562+
; CHECK-LE-NEXT: cmp r0, #0
563563
; CHECK-LE-NEXT: movne r0, #1
564564
; CHECK-LE-NEXT: mov pc, lr
565565
;
566566
; CHECK-V7-LE-LABEL: test_24_8_8:
567567
; CHECK-V7-LE: @ %bb.0:
568568
; CHECK-V7-LE-NEXT: ldrb r0, [r0, #1]
569-
; CHECK-V7-LE-NEXT: lsls r0, r0, #8
569+
; CHECK-V7-LE-NEXT: cmp r0, #0
570570
; CHECK-V7-LE-NEXT: movwne r0, #1
571571
; CHECK-V7-LE-NEXT: bx lr
572572
;
573573
; CHECK-BE-LABEL: test_24_8_8:
574574
; CHECK-BE: @ %bb.0:
575575
; CHECK-BE-NEXT: ldrb r0, [r0, #1]
576-
; CHECK-BE-NEXT: lsls r0, r0, #8
576+
; CHECK-BE-NEXT: cmp r0, #0
577577
; CHECK-BE-NEXT: movne r0, #1
578578
; CHECK-BE-NEXT: mov pc, lr
579579
;
580580
; CHECK-V7-BE-LABEL: test_24_8_8:
581581
; CHECK-V7-BE: @ %bb.0:
582582
; CHECK-V7-BE-NEXT: ldrb r0, [r0, #1]
583-
; CHECK-V7-BE-NEXT: lsls r0, r0, #8
583+
; CHECK-V7-BE-NEXT: cmp r0, #0
584584
; CHECK-V7-BE-NEXT: movwne r0, #1
585585
; CHECK-V7-BE-NEXT: bx lr
586586
%a = load i24, ptr %y
@@ -633,28 +633,28 @@ define i1 @test_24_8_16(ptr %y) {
633633
; CHECK-LE-LABEL: test_24_8_16:
634634
; CHECK-LE: @ %bb.0:
635635
; CHECK-LE-NEXT: ldrb r0, [r0, #2]
636-
; CHECK-LE-NEXT: lsls r0, r0, #16
636+
; CHECK-LE-NEXT: cmp r0, #0
637637
; CHECK-LE-NEXT: movne r0, #1
638638
; CHECK-LE-NEXT: mov pc, lr
639639
;
640640
; CHECK-V7-LE-LABEL: test_24_8_16:
641641
; CHECK-V7-LE: @ %bb.0:
642642
; CHECK-V7-LE-NEXT: ldrb r0, [r0, #2]
643-
; CHECK-V7-LE-NEXT: lsls r0, r0, #16
643+
; CHECK-V7-LE-NEXT: cmp r0, #0
644644
; CHECK-V7-LE-NEXT: movwne r0, #1
645645
; CHECK-V7-LE-NEXT: bx lr
646646
;
647647
; CHECK-BE-LABEL: test_24_8_16:
648648
; CHECK-BE: @ %bb.0:
649649
; CHECK-BE-NEXT: ldrb r0, [r0]
650-
; CHECK-BE-NEXT: lsls r0, r0, #16
650+
; CHECK-BE-NEXT: cmp r0, #0
651651
; CHECK-BE-NEXT: movne r0, #1
652652
; CHECK-BE-NEXT: mov pc, lr
653653
;
654654
; CHECK-V7-BE-LABEL: test_24_8_16:
655655
; CHECK-V7-BE: @ %bb.0:
656656
; CHECK-V7-BE-NEXT: ldrb r0, [r0]
657-
; CHECK-V7-BE-NEXT: lsls r0, r0, #16
657+
; CHECK-V7-BE-NEXT: cmp r0, #0
658658
; CHECK-V7-BE-NEXT: movwne r0, #1
659659
; CHECK-V7-BE-NEXT: bx lr
660660
%a = load i24, ptr %y

‎llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll

Lines changed: 17 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -173,64 +173,61 @@ define void @f6(ptr %a0, i16 %a1) #0 {
173173
; CHECK-LABEL: f6:
174174
; CHECK: // %bb.0: // %b0
175175
; CHECK-NEXT: {
176-
; CHECK-NEXT: r2 = extractu(r1,#8,#8)
177-
; CHECK-NEXT: }
178-
; CHECK-NEXT: {
179-
; CHECK-NEXT: r3 = #255
176+
; CHECK-NEXT: r2 = #255
180177
; CHECK-NEXT: }
181178
; CHECK-NEXT: {
182-
; CHECK-NEXT: p1 = !bitsclr(r1,r3)
179+
; CHECK-NEXT: r3 = ##65280
183180
; CHECK-NEXT: }
184181
; CHECK-NEXT: {
185-
; CHECK-NEXT: p0 = cmp.eq(r2,#0)
182+
; CHECK-NEXT: p1 = !bitsclr(r1,r2)
186183
; CHECK-NEXT: }
187184
; CHECK-NEXT: {
188-
; CHECK-NEXT: if (p0) r2 = #0
185+
; CHECK-NEXT: p0 = !bitsclr(r1,r3)
189186
; CHECK-NEXT: }
190187
; CHECK-NEXT: {
191188
; CHECK-NEXT: r1 = mux(p1,#8,#0)
192189
; CHECK-NEXT: }
193190
; CHECK-NEXT: {
194-
; CHECK-NEXT: r3 = mux(p1,#2,#0)
191+
; CHECK-NEXT: r2 = mux(p1,#2,#0)
195192
; CHECK-NEXT: }
196193
; CHECK-NEXT: {
197-
; CHECK-NEXT: r5 = setbit(r1,#2)
194+
; CHECK-NEXT: r3 = mux(p0,##128,#0)
198195
; CHECK-NEXT: }
199196
; CHECK-NEXT: {
200-
; CHECK-NEXT: r6 = setbit(r3,#0)
197+
; CHECK-NEXT: r4 = mux(p0,#32,#0)
201198
; CHECK-NEXT: }
202199
; CHECK-NEXT: {
203-
; CHECK-NEXT: if (!p0) r2 = #128
200+
; CHECK-NEXT: r5 = setbit(r1,#2)
204201
; CHECK-NEXT: }
205202
; CHECK-NEXT: {
206-
; CHECK-NEXT: r4 = mux(p0,#0,#32)
203+
; CHECK-NEXT: r6 = setbit(r2,#0)
207204
; CHECK-NEXT: }
208205
; CHECK-NEXT: {
209206
; CHECK-NEXT: if (!p1) r5 = add(r1,#0)
210207
; CHECK-NEXT: }
211208
; CHECK-NEXT: {
212-
; CHECK-NEXT: if (!p1) r6 = add(r3,#0)
209+
; CHECK-NEXT: r1 = setbit(r3,#6)
213210
; CHECK-NEXT: }
214211
; CHECK-NEXT: {
215-
; CHECK-NEXT: r1 = setbit(r2,#6)
212+
; CHECK-NEXT: if (!p1) r6 = add(r2,#0)
216213
; CHECK-NEXT: }
217214
; CHECK-NEXT: {
218-
; CHECK-NEXT: r3 = setbit(r4,#4)
215+
; CHECK-NEXT: r2 = setbit(r4,#4)
219216
; CHECK-NEXT: }
220217
; CHECK-NEXT: {
221-
; CHECK-NEXT: r5 = or(r6,r5)
218+
; CHECK-NEXT: if (!p0) r2 = add(r4,#0)
222219
; CHECK-NEXT: }
223220
; CHECK-NEXT: {
224-
; CHECK-NEXT: if (!p0) r2 = add(r1,#0)
221+
; CHECK-NEXT: if (!p0) r1 = add(r3,#0)
225222
; CHECK-NEXT: }
226223
; CHECK-NEXT: {
227-
; CHECK-NEXT: if (!p0) r4 = add(r3,#0)
224+
; CHECK-NEXT: r4 = or(r6,r5)
228225
; CHECK-NEXT: }
229226
; CHECK-NEXT: {
230-
; CHECK-NEXT: r5 |= or(r4,r2)
227+
; CHECK-NEXT: r4 |= or(r2,r1)
231228
; CHECK-NEXT: }
232229
; CHECK-NEXT: {
233-
; CHECK-NEXT: memb(r0+#0) = r5
230+
; CHECK-NEXT: memb(r0+#0) = r4
234231
; CHECK-NEXT: }
235232
; CHECK-NEXT: {
236233
; CHECK-NEXT: jumpr r31

‎llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -534,6 +534,7 @@ define i1 @add_ugecmp_i32_i16(i32 %x) nounwind {
534534
; RV64I-NEXT: lui a1, 8
535535
; RV64I-NEXT: add a0, a0, a1
536536
; RV64I-NEXT: srliw a0, a0, 16
537+
; RV64I-NEXT: slli a0, a0, 16
537538
; RV64I-NEXT: snez a0, a0
538539
; RV64I-NEXT: ret
539540
;

‎llvm/test/CodeGen/RISCV/sextw-removal.ll

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1034,31 +1034,34 @@ define signext i32 @bug(i32 signext %x) {
10341034
; CHECK: # %bb.0: # %entry
10351035
; CHECK-NEXT: beqz a0, .LBB18_4
10361036
; CHECK-NEXT: # %bb.1: # %if.end
1037-
; CHECK-NEXT: srliw a2, a0, 16
1038-
; CHECK-NEXT: seqz a1, a2
1037+
; CHECK-NEXT: srliw a3, a0, 16
1038+
; CHECK-NEXT: seqz a1, a3
10391039
; CHECK-NEXT: slli a1, a1, 4
10401040
; CHECK-NEXT: sllw a1, a0, a1
1041+
; CHECK-NEXT: srliw a2, a1, 24
1042+
; CHECK-NEXT: slli a2, a2, 24
10411043
; CHECK-NEXT: li a0, 16
1042-
; CHECK-NEXT: beqz a2, .LBB18_3
1044+
; CHECK-NEXT: beqz a3, .LBB18_3
10431045
; CHECK-NEXT: # %bb.2: # %if.end
10441046
; CHECK-NEXT: li a0, 32
10451047
; CHECK-NEXT: .LBB18_3: # %if.end
1046-
; CHECK-NEXT: srliw a2, a1, 24
10471048
; CHECK-NEXT: seqz a2, a2
10481049
; CHECK-NEXT: slli a3, a2, 3
10491050
; CHECK-NEXT: sllw a1, a1, a3
1051+
; CHECK-NEXT: srliw a3, a1, 28
1052+
; CHECK-NEXT: slli a3, a3, 28
10501053
; CHECK-NEXT: neg a2, a2
10511054
; CHECK-NEXT: andi a2, a2, -8
10521055
; CHECK-NEXT: add a0, a0, a2
1053-
; CHECK-NEXT: srliw a2, a1, 28
1054-
; CHECK-NEXT: seqz a2, a2
1056+
; CHECK-NEXT: seqz a2, a3
10551057
; CHECK-NEXT: slli a3, a2, 2
10561058
; CHECK-NEXT: sllw a1, a1, a3
1059+
; CHECK-NEXT: srliw a3, a1, 30
1060+
; CHECK-NEXT: slli a3, a3, 30
10571061
; CHECK-NEXT: neg a2, a2
10581062
; CHECK-NEXT: andi a2, a2, -4
10591063
; CHECK-NEXT: add a0, a0, a2
1060-
; CHECK-NEXT: srliw a2, a1, 30
1061-
; CHECK-NEXT: seqz a2, a2
1064+
; CHECK-NEXT: seqz a2, a3
10621065
; CHECK-NEXT: slli a3, a2, 1
10631066
; CHECK-NEXT: sllw a1, a1, a3
10641067
; CHECK-NEXT: neg a2, a2
@@ -1074,31 +1077,34 @@ define signext i32 @bug(i32 signext %x) {
10741077
; NOREMOVAL: # %bb.0: # %entry
10751078
; NOREMOVAL-NEXT: beqz a0, .LBB18_4
10761079
; NOREMOVAL-NEXT: # %bb.1: # %if.end
1077-
; NOREMOVAL-NEXT: srliw a2, a0, 16
1078-
; NOREMOVAL-NEXT: seqz a1, a2
1080+
; NOREMOVAL-NEXT: srliw a3, a0, 16
1081+
; NOREMOVAL-NEXT: seqz a1, a3
10791082
; NOREMOVAL-NEXT: slli a1, a1, 4
10801083
; NOREMOVAL-NEXT: sllw a1, a0, a1
1084+
; NOREMOVAL-NEXT: srliw a2, a1, 24
1085+
; NOREMOVAL-NEXT: slli a2, a2, 24
10811086
; NOREMOVAL-NEXT: li a0, 16
1082-
; NOREMOVAL-NEXT: beqz a2, .LBB18_3
1087+
; NOREMOVAL-NEXT: beqz a3, .LBB18_3
10831088
; NOREMOVAL-NEXT: # %bb.2: # %if.end
10841089
; NOREMOVAL-NEXT: li a0, 32
10851090
; NOREMOVAL-NEXT: .LBB18_3: # %if.end
1086-
; NOREMOVAL-NEXT: srliw a2, a1, 24
10871091
; NOREMOVAL-NEXT: seqz a2, a2
10881092
; NOREMOVAL-NEXT: slli a3, a2, 3
10891093
; NOREMOVAL-NEXT: sllw a1, a1, a3
1094+
; NOREMOVAL-NEXT: srliw a3, a1, 28
1095+
; NOREMOVAL-NEXT: slli a3, a3, 28
10901096
; NOREMOVAL-NEXT: neg a2, a2
10911097
; NOREMOVAL-NEXT: andi a2, a2, -8
10921098
; NOREMOVAL-NEXT: add a0, a0, a2
1093-
; NOREMOVAL-NEXT: srliw a2, a1, 28
1094-
; NOREMOVAL-NEXT: seqz a2, a2
1099+
; NOREMOVAL-NEXT: seqz a2, a3
10951100
; NOREMOVAL-NEXT: slli a3, a2, 2
10961101
; NOREMOVAL-NEXT: sllw a1, a1, a3
1102+
; NOREMOVAL-NEXT: srliw a3, a1, 30
1103+
; NOREMOVAL-NEXT: slli a3, a3, 30
10971104
; NOREMOVAL-NEXT: neg a2, a2
10981105
; NOREMOVAL-NEXT: andi a2, a2, -4
10991106
; NOREMOVAL-NEXT: add a0, a0, a2
1100-
; NOREMOVAL-NEXT: srliw a2, a1, 30
1101-
; NOREMOVAL-NEXT: seqz a2, a2
1107+
; NOREMOVAL-NEXT: seqz a2, a3
11021108
; NOREMOVAL-NEXT: slli a3, a2, 1
11031109
; NOREMOVAL-NEXT: sllw a1, a1, a3
11041110
; NOREMOVAL-NEXT: neg a2, a2

‎llvm/test/CodeGen/RISCV/signed-truncation-check.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,7 @@ define i1 @add_ultcmp_i32_i16(i32 %x) nounwind {
586586
; RV64I-NEXT: lui a1, 8
587587
; RV64I-NEXT: add a0, a0, a1
588588
; RV64I-NEXT: srliw a0, a0, 16
589+
; RV64I-NEXT: slli a0, a0, 16
589590
; RV64I-NEXT: seqz a0, a0
590591
; RV64I-NEXT: ret
591592
;

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