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llvm-reduce: Add pass to remove register uses
Try to delete implicit uses, and add undef flags to explicit ones.
1 parent 81edc83 commit 47c8ec8

12 files changed

+159
-7
lines changed

‎llvm/test/tools/llvm-reduce/mir/generic-vreg.mir

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@@ -22,7 +22,7 @@
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# RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
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# RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
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# RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1)
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# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %{{[0-9]+}}(<2 x s16>), implicit %{{[0-9]+}}(s64)
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# RESULT-NEXT: S_ENDPGM 0{{$}}
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---
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name: f

‎llvm/test/tools/llvm-reduce/mir/instr-reduce.mir

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# RUN: llvm-reduce -mtriple=riscv32 --test %python --test-arg %p/instr-reduce.py %s -o %t
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# RUN: llvm-reduce --delta-passes=instructions -mtriple=riscv32 --test %python --test-arg %p/instr-reduce.py %s -o %t
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# RUN: cat %t | FileCheck --match-full-lines %s
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# REQUIRES: riscv-registered-target

‎llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-riscv.mir

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@@ -1,5 +1,5 @@
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# REQUIRES: riscv-registered-target
2-
# RUN: llvm-reduce -simplify-mir -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: llvm-reduce -simplify-mir --delta-passes=instructions -mtriple=riscv64-- --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: ADDW

‎llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir

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@@ -1,5 +1,5 @@
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# REQUIRES: amdgpu-registered-target
2-
# RUN: llvm-reduce -simplify-mir -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: llvm-reduce -simplify-mir --delta-passes=instruction-flags -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: V_ADD_F32

‎llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir

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# REQUIRES: amdgpu-registered-target
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# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: V_MUL_F32_e32 %vgpr0
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# CHECK-INTERESTINGNESS: V_MUL_F32_e32 {{.*}}%vgpr1, %vgpr0
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# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr0
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# CHECK-INTERESTINGNESS: SI_CALL {{.*}}$vgpr3
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# RESULT: %mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, undef %vgpr1, implicit $mode, implicit $exec
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# RESULT: %mul1:vgpr_32 = V_MUL_F32_e32 undef %vgpr1, %vgpr0, implicit $mode, implicit $exec
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# RESULT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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# RESULT: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
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# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr0
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# RESULT: $sgpr30_sgpr31 = SI_CALL undef %call_target, @callee, csr_amdgpu, implicit $vgpr3
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# RESULT: %impdef:vreg_64 = IMPLICIT_DEF
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# RESULT: GLOBAL_STORE_DWORD undef %ptr, undef %impdef.sub1, 0, 0, implicit $exec
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# RESULT: undef %impdef.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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# RESULT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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# RESULT: S_BARRIER
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# RESULT: S_ENDPGM 0
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--- |
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define void @func() {
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ret void
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}
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declare void @callee()
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...
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---
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name: func
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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S_WAITCNT 0
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%vgpr0:vgpr_32 = COPY $vgpr0
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%vgpr1:vgpr_32 = COPY $vgpr1
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%mul0:vgpr_32 = V_MUL_F32_e32 %vgpr0, %vgpr1, implicit $mode, implicit $exec
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%mul1:vgpr_32 = V_MUL_F32_e32 %vgpr1, %vgpr0, implicit $mode, implicit $exec
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%call_target:sreg_64 = IMPLICIT_DEF
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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$vgpr1 = V_MOV_B32_e32 1, implicit $exec
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$sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr0, implicit $vgpr1
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$vgpr2 = V_MOV_B32_e32 2, implicit $exec
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$vgpr3 = V_MOV_B32_e32 3, implicit $exec
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$sgpr30_sgpr31 = SI_CALL %call_target, @callee, csr_amdgpu, implicit $vgpr2, implicit $vgpr3
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%impdef:vreg_64 = IMPLICIT_DEF
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%ptr:vreg_64 = IMPLICIT_DEF
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GLOBAL_STORE_DWORD %ptr, %impdef.sub1, 0, 0, implicit $exec
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%impdef.sub0 = V_MOV_B32_e32 0, implicit $exec
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$scc = IMPLICIT_DEF
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.1:
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S_BARRIER
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S_ENDPGM 0, implicit %mul0, implicit %mul1
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...
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‎llvm/test/tools/llvm-reduce/mir/subreg-def0.mir

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@@ -1,5 +1,5 @@
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# REQUIRES: amdgpu-registered-target
2-
# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
2+
# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: V_ADD_U32

‎llvm/test/tools/llvm-reduce/mir/subreg-def1.mir

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@@ -1,5 +1,5 @@
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# REQUIRES: amdgpu-registered-target
2-
# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
2+
# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec

‎llvm/test/tools/llvm-reduce/mir/undef-virt-reg.mir

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@@ -1,5 +1,5 @@
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# REQUIRES: amdgpu-registered-target
2-
# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: llvm-reduce --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
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# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
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# CHECK-INTERESTINGNESS: S_NOP 0

‎llvm/tools/llvm-reduce/CMakeLists.txt

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@@ -42,6 +42,7 @@ add_llvm_tool(llvm-reduce
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deltas/ReduceInstructionFlagsMIR.cpp
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deltas/ReduceIRReferences.cpp
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deltas/ReduceVirtualRegisters.cpp
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deltas/ReduceRegisterUses.cpp
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llvm-reduce.cpp
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DEPENDS

‎llvm/tools/llvm-reduce/DeltaManager.cpp

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#include "deltas/ReduceOperands.h"
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#include "deltas/ReduceOperandsSkip.h"
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#include "deltas/ReduceOperandsToArgs.h"
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#include "deltas/ReduceRegisterUses.h"
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#include "deltas/ReduceSpecialGlobals.h"
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#include "deltas/ReduceVirtualRegisters.h"
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#include "llvm/Support/CommandLine.h"
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DELTA_PASS("ir-block-references", reduceIRBlockReferencesDeltaPass) \
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DELTA_PASS("ir-function-references", reduceIRFunctionReferencesDeltaPass) \
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DELTA_PASS("instruction-flags", reduceInstructionFlagsMIRDeltaPass) \
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DELTA_PASS("register-uses", reduceRegisterUsesMIRDeltaPass) \
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DELTA_PASS("register-hints", reduceVirtualRegisterHintsDeltaPass)
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static void runAllDeltaPasses(TestRunner &Tester) {

‎llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp

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//===- ReduceRegisterUses.cpp - Specialized Delta Pass --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a function which calls the Generic Delta pass in order
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// to reduce uninteresting register uses from the MachineFunction.
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//
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//===----------------------------------------------------------------------===//
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#include "ReduceRegisterUses.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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static void removeUsesFromFunction(Oracle &O, MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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int NumOperands = MI.getNumOperands();
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int NumRequiredOps = MI.getNumExplicitOperands() +
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MI.getDesc().getNumImplicitDefs() +
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MI.getDesc().getNumImplicitUses();
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for (int I = NumOperands - 1; I >= 0; --I) {
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MachineOperand &MO = MI.getOperand(I);
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if (!MO.isReg() || !MO.readsReg())
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continue;
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Register Reg = MO.getReg();
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if (Reg.isPhysical() && MRI.isReserved(Reg))
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continue;
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if (O.shouldKeep())
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continue;
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// Remove implicit operands. If the register is part of the fixed
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// operand list, set to undef.
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if (I >= NumRequiredOps)
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MI.removeOperand(I);
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else
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MO.setIsUndef();
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}
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}
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}
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}
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static void removeUsesFromModule(Oracle &O, ReducerWorkItem &WorkItem) {
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for (const Function &F : WorkItem.getModule()) {
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if (auto *MF = WorkItem.MMI->getMachineFunction(F))
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removeUsesFromFunction(O, *MF);
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}
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}
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void llvm::reduceRegisterUsesMIRDeltaPass(TestRunner &Test) {
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outs() << "*** Reducing register uses...\n";
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runDeltaPass(Test, removeUsesFromModule);
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}

‎llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.h

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//===- ReduceRegisterUses.h - Specialized Delta Pass -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a function which calls the Generic Delta pass in order
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// to reduce uninteresting register uses from the MachineFunction.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEREGISTERUSES_H
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#define LLVM_TOOLS_LLVM_REDUCE_DELTAS_REDUCEREGISTERUSES_H
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#include "Delta.h"
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namespace llvm {
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void reduceRegisterUsesMIRDeltaPass(TestRunner &Test);
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} // namespace llvm
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#endif

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