Addressed PR comments

Author: michaelselehov

llvm/lib/CodeGen/MachineLICM.cpp

@@ -1264,21 +1264,21 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI,
 
   // If we have a COPY with other uses in the loop, hoist to allow the users to
   // also be hoisted.
-  Register defReg;
+  Register DefReg;
   if (MI.isCopy() && MI.getOperand(0).isReg() &&
-      (defReg = MI.getOperand(0).getReg()).isVirtual() &&
+      (DefReg = MI.getOperand(0).getReg()).isVirtual() &&
       MI.getOperand(1).isReg() && MI.getOperand(1).getReg().isVirtual() &&
       IsLoopInvariantInst(MI, CurLoop) &&
       any_of(MRI->use_nodbg_instructions(MI.getOperand(0).getReg()),
-             [&CurLoop, this, defReg, Cost](MachineInstr &UseMI) {
+             [&CurLoop, this, DefReg, Cost](MachineInstr &UseMI) {
                if (!CurLoop->contains(&UseMI))
                  return false;
 
                // COPY is a cheap instruction, but if moving it won't cause high
                // RP we're fine to hoist it even if the user can't be hoisted
                // later Otherwise we want to check the user if it's hoistable
                if (CanCauseHighRegPressure(Cost, false) &&
-                   !CurLoop->isLoopInvariant(UseMI, defReg))
+                   !CurLoop->isLoopInvariant(UseMI, DefReg))
                  return false;
 
                return true;

llvm/test/CodeGen/AMDGPU/copy-hoist-no-spills.ll

@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; NOTE: There must be no spill reload inside the loop starting with LBB0_1:
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O2 -vectorize-loops -vectorize-slp -amdgpu-early-inline-all=true -amdgpu-function-calls=false < %s | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-p9:192:256:256:32"
 target triple = "amdgcn-amd-amdhsa"