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1 parent 15de77d commit 487a070Copy full SHA for 487a070
llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
@@ -73,3 +73,26 @@ define i32 @modwu(i64 %a, i64 %b) {
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%r = urem i32 %conv1, %conv2
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ret i32 %r
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}
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+
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+define signext i32 @sextw_rmv(i32 signext %a, i32 signext %b, i32 signext %c) {
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+; LA64-LABEL: sextw_rmv:
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+; LA64: # %bb.0: # %entry
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+; LA64-NEXT: mul.w $a0, $a1, $a0
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+; LA64-NEXT: div.w $a1, $a2, $a0
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+; LA64-NEXT: sltu $a0, $a1, $a0
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+; LA64-NEXT: ret
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+;
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+; LA64-DIV32-LABEL: sextw_rmv:
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+; LA64-DIV32: # %bb.0: # %entry
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+; LA64-DIV32-NEXT: mul.d $a0, $a1, $a0
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+; LA64-DIV32-NEXT: addi.w $a1, $a0, 0
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+; LA64-DIV32-NEXT: div.w $a0, $a2, $a0
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+; LA64-DIV32-NEXT: sltu $a0, $a0, $a1
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+; LA64-DIV32-NEXT: ret
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+entry:
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+ %mul = mul nsw i32 %b, %a
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+ %div = sdiv i32 %c, %mul
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+ %cmp = icmp ult i32 %div, %mul
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+ %conv = zext i1 %cmp to i32
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+ ret i32 %conv
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+}
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