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[RegisterCoalescer] Fix issue in the RegisterCoalescer.
Two tests are added to this fix. The X86 test fails without the patch. The PowerPC test passes with and without the patch but is added as a way track future possible failures when register classes are changed in a future patch.
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‎llvm/lib/CodeGen/RegisterCoalescer.cpp

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@@ -3671,6 +3671,14 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
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// having stale segments.
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LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
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LHSVals.pruneSubRegValues(LHS, ShrinkMask);
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RHSVals.pruneSubRegValues(LHS, ShrinkMask);
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} else if (TrackSubRegLiveness && !CP.getDstIdx() && CP.getSrcIdx()) {
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LHS.createSubRangeFrom(LIS->getVNInfoAllocator(),
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CP.getNewRC()->getLaneMask(), LHS);
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mergeSubRangeInto(LHS, RHS, TRI->getSubRegIndexLaneMask(CP.getSrcIdx()), CP,
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CP.getDstIdx());
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LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
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LHSVals.pruneSubRegValues(LHS, ShrinkMask);
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RHSVals.pruneSubRegValues(LHS, ShrinkMask);
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}

‎llvm/test/CodeGen/PowerPC/subreg-coalescer.mir

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# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
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# RUN: -verify-machineinstrs --run-pass=register-coalescer -o - | FileCheck %s
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---
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name: check_subregs
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3
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%0:g8rc_and_g8rc_nox0 = COPY $x3
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%3:f8rc, %4:g8rc_and_g8rc_nox0 = LFSUX %0, %0
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%5:f4rc = FRSP killed %3, implicit $rm
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%22:vslrc = SUBREG_TO_REG 1, %5, %subreg.sub_64
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%11:vrrc = XVCVDPSP killed %22, implicit $rm
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$v2 = COPY %11
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BLR8 implicit $lr8, implicit $rm, implicit $v2
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...
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# CHECK: %0:g8rc_and_g8rc_nox0 = COPY $x3
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# CHECK-NEXT: %1:f8rc, dead %2:g8rc_and_g8rc_nox0 = LFSUX %0, %0
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# CHECK-NEXT: undef %4.sub_64:vslrc = FRSP %1, implicit $rm
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# CHECK-NEXT: %5:vrrc = XVCVDPSP %4, implicit $rm
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# CHECK-NEXT: $v2 = COPY %5
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# CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2

‎llvm/test/CodeGen/X86/subreg-fail.mir

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# RUN: llc -mtriple x86_64-unknown-unknown -x mir < %s \
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# RUN: -verify-machineinstrs -enable-subreg-liveness=true \
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# RUN: --run-pass=register-coalescer -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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%pair = type { i64, double }
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%t21 = type { ptr }
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%t13 = type { ptr, %t15, %t15 }
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%t15 = type { i8, i32, i32 }
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@__force_order = external hidden global i32, align 4
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@.str = private unnamed_addr constant { [1 x i8], [63 x i8] } zeroinitializer, align 32
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@a = external global i32, align 4
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@fn1.g = private unnamed_addr constant [9 x ptr] [ptr null, ptr @a, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null, ptr null], align 16
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@e = external global i32, align 4
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@__stack_chk_guard = external dso_local global ptr
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; Function Attrs: nounwind ssp
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define i32 @test1() #0 {
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entry:
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%tmp5.i = load volatile i32, ptr undef, align 4
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%conv.i = zext i32 %tmp5.i to i64
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%tmp12.i = load volatile i32, ptr undef, align 4
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%conv13.i = zext i32 %tmp12.i to i64
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%shl.i = shl i64 %conv13.i, 32
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%or.i = or i64 %shl.i, %conv.i
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%add16.i = add i64 %or.i, 256
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%shr.i = lshr i64 %add16.i, 8
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%conv19.i = trunc i64 %shr.i to i32
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store volatile i32 %conv19.i, ptr undef, align 4
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ret i32 undef
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}
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...
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---
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name: test1
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: true
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gr32, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64_nosp, preferred-register: '' }
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- { id: 3, class: gr32, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: gr64, preferred-register: '' }
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- { id: 7, class: gr64, preferred-register: '' }
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- { id: 8, class: gr64, preferred-register: '' }
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- { id: 9, class: gr32, preferred-register: '' }
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- { id: 10, class: gr64, preferred-register: '' }
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- { id: 11, class: gr32, preferred-register: '' }
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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isCalleeSavedInfoValid: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo:
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amxProgModel: None
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body: |
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bb.0.entry:
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%0:gr32 = MOV32rm undef %1:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`)
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%2:gr64_nosp = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit
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%3:gr32 = MOV32rm undef %4:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`)
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%5:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit
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%6:gr64 = COPY killed %5
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%6:gr64 = SHL64ri %6, 32, implicit-def dead $eflags
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%7:gr64 = LEA64r killed %6, 1, killed %2, 256, $noreg
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%8:gr64 = COPY killed %7
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%8:gr64 = SHR64ri %8, 8, implicit-def dead $eflags
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%9:gr32 = COPY killed %8.sub_32bit
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MOV32mr undef %10:gr64, 1, $noreg, 0, $noreg, killed %9 :: (volatile store (s32) into `ptr undef`)
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RET 0, undef $eax
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...
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# CHECK: undef %2.sub_32bit:gr64_nosp = MOV32rm undef %1:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`)
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# CHECK-NEXT: undef %6.sub_32bit:gr64_with_sub_8bit = MOV32rm undef %4:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`)
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# CHECK-NEXT: %6:gr64_with_sub_8bit = SHL64ri %6, 32, implicit-def dead $eflags
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# CHECK-NEXT: %8:gr64_with_sub_8bit = LEA64r %6, 1, %2, 256, $noreg
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# CHECK-NEXT: %8:gr64_with_sub_8bit = SHR64ri %8, 8, implicit-def dead $eflags
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# CHECK-NEXT: MOV32mr undef %10:gr64, 1, $noreg, 0, $noreg, %8.sub_32bit :: (volatile store (s32) into `ptr undef`)
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# CHECK-NEXT: RET 0, undef $eax
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