[Clang][CodeGen][UBSan] Add pre-commit tests. NFC.

Author: dtcxzyw

clang/test/CodeGen/ubsan-attr.cpp

@@ -0,0 +1,84 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 5
+// RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -fsanitize=signed-integer-overflow -O3 %s -o - -fsanitize-recover=signed-integer-overflow | FileCheck %s --check-prefixes=RECOVER
+// RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -fsanitize=signed-integer-overflow -O3 %s -o - | FileCheck %s --check-prefixes=ABORT
+
+// RECOVER: Function Attrs: mustprogress nounwind
+// RECOVER-LABEL: define dso_local noundef range(i32 -32768, 32768) i32 @_Z4testRiRs(
+// RECOVER-SAME: ptr noundef nonnull align 4 captures(none) dereferenceable(4) [[A:%.*]], ptr noundef nonnull readonly align 2 captures(none) dereferenceable(2) [[C:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// RECOVER-NEXT:  [[ENTRY:.*]]:
+// RECOVER-NEXT:    [[TMP0:%.*]] = load i16, ptr [[C]], align 2, !tbaa [[TBAA2:![0-9]+]]
+// RECOVER-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
+// RECOVER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !tbaa [[TBAA6:![0-9]+]]
+// RECOVER-NEXT:    [[TMP2:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP1]], i32 [[CONV]]), !nosanitize [[META8:![0-9]+]]
+// RECOVER-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META8]]
+// RECOVER-NEXT:    br i1 [[TMP3]], label %[[HANDLER_ADD_OVERFLOW:.*]], label %[[CONT:.*]], !prof [[PROF9:![0-9]+]], !nosanitize [[META8]]
+// RECOVER:       [[HANDLER_ADD_OVERFLOW]]:
+// RECOVER-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META8]]
+// RECOVER-NEXT:    [[TMP5:%.*]] = zext i32 [[CONV]] to i64, !nosanitize [[META8]]
+// RECOVER-NEXT:    tail call void @__ubsan_handle_add_overflow(ptr nonnull @[[GLOB1]], i64 [[TMP4]], i64 [[TMP5]]) #[[ATTR3:[0-9]+]], !nosanitize [[META8]]
+// RECOVER-NEXT:    [[DOTPRE:%.*]] = load i16, ptr [[C]], align 2, !tbaa [[TBAA2]]
+// RECOVER-NEXT:    [[DOTPRE3:%.*]] = sext i16 [[DOTPRE]] to i32
+// RECOVER-NEXT:    br label %[[CONT]], !nosanitize [[META8]]
+// RECOVER:       [[CONT]]:
+// RECOVER-NEXT:    [[CONV1_PRE_PHI:%.*]] = phi i32 [ [[DOTPRE3]], %[[HANDLER_ADD_OVERFLOW]] ], [ [[CONV]], %[[ENTRY]] ]
+// RECOVER-NEXT:    [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META8]]
+// RECOVER-NEXT:    store i32 [[TMP6]], ptr [[A]], align 4, !tbaa [[TBAA6]]
+// RECOVER-NEXT:    ret i32 [[CONV1_PRE_PHI]]
+//
+// ABORT: Function Attrs: mustprogress nounwind
+// ABORT-LABEL: define dso_local noundef range(i32 -32768, 32768) i32 @_Z4testRiRs(
+// ABORT-SAME: ptr noundef nonnull align 4 captures(none) dereferenceable(4) [[A:%.*]], ptr noundef nonnull readonly align 2 captures(none) dereferenceable(2) [[C:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// ABORT-NEXT:  [[ENTRY:.*:]]
+// ABORT-NEXT:    [[TMP0:%.*]] = load i16, ptr [[C]], align 2, !tbaa [[TBAA2:![0-9]+]]
+// ABORT-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
+// ABORT-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !tbaa [[TBAA6:![0-9]+]]
+// ABORT-NEXT:    [[TMP2:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP1]], i32 [[CONV]]), !nosanitize [[META8:![0-9]+]]
+// ABORT-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META8]]
+// ABORT-NEXT:    br i1 [[TMP3]], label %[[HANDLER_ADD_OVERFLOW:.*]], label %[[CONT:.*]], !prof [[PROF9:![0-9]+]], !nosanitize [[META8]]
+// ABORT:       [[HANDLER_ADD_OVERFLOW]]:
+// ABORT-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META8]]
+// ABORT-NEXT:    [[TMP5:%.*]] = zext i32 [[CONV]] to i64, !nosanitize [[META8]]
+// ABORT-NEXT:    tail call void @__ubsan_handle_add_overflow_abort(ptr nonnull @[[GLOB1]], i64 [[TMP4]], i64 [[TMP5]]) #[[ATTR3:[0-9]+]], !nosanitize [[META8]]
+// ABORT-NEXT:    unreachable, !nosanitize [[META8]]
+// ABORT:       [[CONT]]:
+// ABORT-NEXT:    [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META8]]
+// ABORT-NEXT:    store i32 [[TMP6]], ptr [[A]], align 4, !tbaa [[TBAA6]]
+// ABORT-NEXT:    ret i32 [[CONV]]
+//
+int test(int &a, short &c) {
+  a += c;
+  return c;
+}
+//.
+// RECOVER: attributes #[[ATTR0]] = { mustprogress nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
+// RECOVER: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+// RECOVER: attributes #[[ATTR2:[0-9]+]] = { uwtable }
+// RECOVER: attributes #[[ATTR3]] = { nomerge nounwind }
+//.
+// ABORT: attributes #[[ATTR0]] = { mustprogress nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
+// ABORT: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+// ABORT: attributes #[[ATTR2:[0-9]+]] = { noreturn nounwind uwtable }
+// ABORT: attributes #[[ATTR3]] = { nomerge noreturn nounwind }
+//.
+// RECOVER: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// RECOVER: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
+// RECOVER: [[TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
+// RECOVER: [[META3]] = !{!"short", [[META4:![0-9]+]], i64 0}
+// RECOVER: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
+// RECOVER: [[META5]] = !{!"Simple C++ TBAA"}
+// RECOVER: [[TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
+// RECOVER: [[META7]] = !{!"int", [[META4]], i64 0}
+// RECOVER: [[META8]] = !{}
+// RECOVER: [[PROF9]] = !{!"branch_weights", i32 1, i32 1048575}
+//.
+// ABORT: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// ABORT: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
+// ABORT: [[TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
+// ABORT: [[META3]] = !{!"short", [[META4:![0-9]+]], i64 0}
+// ABORT: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
+// ABORT: [[META5]] = !{!"Simple C++ TBAA"}
+// ABORT: [[TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
+// ABORT: [[META7]] = !{!"int", [[META4]], i64 0}
+// ABORT: [[META8]] = !{}
+// ABORT: [[PROF9]] = !{!"branch_weights", i32 1, i32 1048575}
+//.