fixup: constrain reg class instead of convert

Author: SamTebbs33

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -1112,23 +1112,6 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
   default:
     break;
 
-  case AArch64::ConvertPNRtoPPR: {
-    auto TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
-    MachineOperand DstMO = MI.getOperand(0);
-    MachineOperand SrcMO = MI.getOperand(1);
-    unsigned SrcReg = SrcMO.getReg();
-    if (!TRI->isSubRegister(DstMO.getReg(), SrcReg)) {
-      unsigned SrcSuperReg = TRI->getMatchingSuperReg(SrcReg, AArch64::psub,
-                                                      &AArch64::PPRRegClass);
-      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORR_PPzPP))
-          .add(DstMO)
-          .addReg(SrcSuperReg)
-          .addReg(SrcSuperReg)
-          .addReg(SrcSuperReg);
-    }
-    MI.eraseFromParent();
-    return true;
-  }
   case AArch64::BSPv8i8:
   case AArch64::BSPv16i8: {
     Register DstReg = MI.getOperand(0).getReg();

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -4805,7 +4805,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   bool Offset = true;
   MCRegister PNRReg = MCRegister::NoRegister;
   unsigned StackID = TargetStackID::Default;
-  const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
   switch (TRI->getSpillSize(*RC)) {
   case 1:
     if (AArch64::FPR8RegClass.hasSubClassEq(RC))
@@ -4823,12 +4822,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
       assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
              "Unexpected register store without SVE2p1 or SME2");
       if (SrcReg.isVirtual()) {
-        auto NewSrcReg =
-            MF.getRegInfo().createVirtualRegister(&AArch64::PPR_p8to15RegClass);
-        BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ConvertPNRtoPPR),
-                NewSrcReg)
-            .addReg(SrcReg);
-        SrcReg = NewSrcReg;
+        MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::PPRRegClass);
       } else
         SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
       Opc = AArch64::STR_PXI;
@@ -5008,7 +5002,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
              "Unexpected register load without SVE2p1 or SME2");
       PNRReg = DestReg;
       if (DestReg.isVirtual())
-        DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
+        MF.getRegInfo().constrainRegClass(DestReg, &AArch64::PPRRegClass);
       else
         DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
       Opc = AArch64::LDR_PXI;

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -2313,8 +2313,6 @@ let Predicates = [HasBF16, HasSVEorSME] in {
   defm BFCVTNT_ZPmZ : sve_bfloat_convert<0b0, "bfcvtnt", int_aarch64_sve_fcvtnt_bf16f32>;
 } // End HasBF16, HasSVEorSME
 
-def ConvertPNRtoPPR : Pseudo<(outs PPRAny:$Pd), (ins PNRAny:$Pm), []>, Sched<[]>;
-
 let Predicates = [HasSVEorSME] in {
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",

llvm/test/CodeGen/AArch64/spillfill-sve-different-predicate.mir

@@ -213,10 +213,9 @@ body:             |
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr
     ; EXPAND: renamable $pn8 = WHILEGE_CXX_B
-    ; EXPAND: STR_PXI killed renamable $p8, $sp, 7
+    ; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
     ;
-    ; EXPAND: renamable $p0 = LDR_PXI $sp, 7
-    ; EXPAND: $p8 = ORR_PPzPP $p0, $p0, killed $p0, implicit-def $pn8
+    ; EXPAND: renamable $pn8 = LDR_PXI $sp, 7
     ; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0