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Simplify approach by prepending target guard with "sve," or "sme,"
1 parent bfa1348 commit 49c3ed3

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12 files changed

+3460
-3526
lines changed

12 files changed

+3460
-3526
lines changed

‎clang/lib/Sema/SemaARM.cpp

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -569,20 +569,15 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
569569
if (BuiltinType == SemaARM::VerifyRuntimeMode) {
570570
llvm::StringMap<bool> CallerFeatureMapWithoutSVE;
571571
S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSVE, FD);
572-
for (StringRef Feat : {"sve", "sve2", "sve2p1", "sve2-aes", "sve2-sha3",
573-
"sve2-sm4", "sve2-bitperm"})
574-
CallerFeatureMapWithoutSVE[Feat] = false;
572+
CallerFeatureMapWithoutSVE["sve"] = false;
575573

576574
// Avoid emitting diagnostics for a function that can never compile.
577575
if (FnType == SemaARM::ArmStreaming && !CallerFeatureMapWithoutSVE["sme"])
578576
return false;
579577

580578
llvm::StringMap<bool> CallerFeatureMapWithoutSME;
581579
S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSME, FD);
582-
for (StringRef Feat :
583-
{"sme", "sme2", "sme2p1", "sme-f64f64", "sme-i16i64", "sme-b16b16",
584-
"sme-f16f16", "sme-f8f32", "sme-f8f16"})
585-
CallerFeatureMapWithoutSME[Feat] = false;
580+
CallerFeatureMapWithoutSME["sme"] = false;
586581

587582
// We know the builtin requires either some combination of SVE flags, or
588583
// some combination of SME flags, but we need to figure out which part

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22

33
// REQUIRES: aarch64-registered-target
44

5-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
5+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
88

99
#include <arm_sme.h>
1010

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_zero_zt.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22

33
// REQUIRES: aarch64-registered-target
44

5-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7-
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
5+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7+
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
88

99
#include <arm_sme.h>
1010

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,22 +6,22 @@
66

77
void test_features(uint32_t slice, svfloat16x2_t zn2, svfloat16x4_t zn4,
88
svbfloat16x2_t bzn2, svbfloat16x4_t bzn4) __arm_streaming __arm_inout("za") {
9-
// expected-error@+1 {{'svadd_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}}
9+
// expected-error@+1 {{'svadd_za16_f16_vg1x2' needs target feature sme,(sme-f16f16|sme-f8f16)}}
1010
svadd_za16_f16_vg1x2(slice, zn2);
11-
// expected-error@+1 {{'svadd_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}}
11+
// expected-error@+1 {{'svadd_za16_f16_vg1x4' needs target feature sme,(sme-f16f16|sme-f8f16)}}
1212
svadd_za16_f16_vg1x4(slice, zn4);
13-
// expected-error@+1 {{'svsub_za16_f16_vg1x2' needs target feature sme-f16f16|sme-f8f16}}
13+
// expected-error@+1 {{'svsub_za16_f16_vg1x2' needs target feature sme,(sme-f16f16|sme-f8f16)}}
1414
svsub_za16_f16_vg1x2(slice, zn2);
15-
// expected-error@+1 {{'svsub_za16_f16_vg1x4' needs target feature sme-f16f16|sme-f8f16}}
15+
// expected-error@+1 {{'svsub_za16_f16_vg1x4' needs target feature sme,(sme-f16f16|sme-f8f16)}}
1616
svsub_za16_f16_vg1x4(slice, zn4);
1717

18-
// expected-error@+1 {{'svadd_za16_bf16_vg1x2' needs target feature sme-b16b16}}
18+
// expected-error@+1 {{'svadd_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
1919
svadd_za16_bf16_vg1x2(slice, bzn2);
20-
// expected-error@+1 {{'svadd_za16_bf16_vg1x4' needs target feature sme-b16b16}}
20+
// expected-error@+1 {{'svadd_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
2121
svadd_za16_bf16_vg1x4(slice, bzn4);
22-
// expected-error@+1 {{'svsub_za16_bf16_vg1x2' needs target feature sme-b16b16}}
22+
// expected-error@+1 {{'svsub_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
2323
svsub_za16_bf16_vg1x2(slice, bzn2);
24-
// expected-error@+1 {{'svsub_za16_bf16_vg1x4' needs target feature sme-b16b16}}
24+
// expected-error@+1 {{'svsub_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
2525
svsub_za16_bf16_vg1x4(slice, bzn4);
2626
}
2727

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_b16b16.cpp

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -6,45 +6,45 @@
66

77
void test_b16b16( svbfloat16_t bf16, svbfloat16x2_t bf16x2, svbfloat16x4_t bf16x4) __arm_streaming
88
{
9-
// expected-error@+1 {{'svclamp_single_bf16_x2' needs target feature sme2,sve-b16b16}}
9+
// expected-error@+1 {{'svclamp_single_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
1010
svclamp_single_bf16_x2(bf16x2, bf16, bf16);
11-
// expected-error@+1 {{'svclamp_single_bf16_x4' needs target feature sme2,sve-b16b16}}
11+
// expected-error@+1 {{'svclamp_single_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
1212
svclamp_single_bf16_x4(bf16x4, bf16, bf16);
1313

14-
// expected-error@+1 {{'svmax_single_bf16_x2' needs target feature sme2,sve-b16b16}}
14+
// expected-error@+1 {{'svmax_single_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
1515
svmax_single_bf16_x2(bf16x2, bf16);
16-
// expected-error@+1 {{'svmax_single_bf16_x4' needs target feature sme2,sve-b16b16}}
16+
// expected-error@+1 {{'svmax_single_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
1717
svmax_single_bf16_x4(bf16x4, bf16);
18-
// expected-error@+1 {{'svmax_bf16_x2' needs target feature sme2,sve-b16b16}}
18+
// expected-error@+1 {{'svmax_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
1919
svmax_bf16_x2(bf16x2, bf16x2);
20-
// expected-error@+1 {{'svmax_bf16_x4' needs target feature sme2,sve-b16b16}}
20+
// expected-error@+1 {{'svmax_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
2121
svmax_bf16_x4(bf16x4, bf16x4);
2222

23-
// expected-error@+1 {{'svmaxnm_single_bf16_x2' needs target feature sme2,sve-b16b16}}
23+
// expected-error@+1 {{'svmaxnm_single_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
2424
svmaxnm_single_bf16_x2(bf16x2, bf16);
25-
// expected-error@+1 {{'svmaxnm_single_bf16_x4' needs target feature sme2,sve-b16b16}}
25+
// expected-error@+1 {{'svmaxnm_single_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
2626
svmaxnm_single_bf16_x4(bf16x4, bf16);
27-
// expected-error@+1 {{'svmaxnm_bf16_x2' needs target feature sme2,sve-b16b16}}
27+
// expected-error@+1 {{'svmaxnm_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
2828
svmaxnm_bf16_x2(bf16x2, bf16x2);
29-
// expected-error@+1 {{'svmaxnm_bf16_x4' needs target feature sme2,sve-b16b16}}
29+
// expected-error@+1 {{'svmaxnm_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
3030
svmaxnm_bf16_x4(bf16x4, bf16x4);
3131

32-
// expected-error@+1 {{'svmin_single_bf16_x2' needs target feature sme2,sve-b16b16}}
32+
// expected-error@+1 {{'svmin_single_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
3333
svmin_single_bf16_x2(bf16x2, bf16);
34-
// expected-error@+1 {{'svmin_single_bf16_x4' needs target feature sme2,sve-b16b16}}
34+
// expected-error@+1 {{'svmin_single_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
3535
svmin_single_bf16_x4(bf16x4, bf16);
36-
// expected-error@+1 {{'svmin_bf16_x2' needs target feature sme2,sve-b16b16}}
36+
// expected-error@+1 {{'svmin_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
3737
svmin_bf16_x2(bf16x2, bf16x2);
38-
// expected-error@+1 {{'svmin_bf16_x4' needs target feature sme2,sve-b16b16}}
38+
// expected-error@+1 {{'svmin_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
3939
svmin_bf16_x4(bf16x4, bf16x4);
4040

41-
// expected-error@+1 {{'svminnm_single_bf16_x2' needs target feature sme2,sve-b16b16}}
41+
// expected-error@+1 {{'svminnm_single_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
4242
svminnm_single_bf16_x2(bf16x2, bf16);
43-
// expected-error@+1 {{'svminnm_single_bf16_x4' needs target feature sme2,sve-b16b16}}
43+
// expected-error@+1 {{'svminnm_single_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
4444
svminnm_single_bf16_x4(bf16x4, bf16);
4545

46-
// expected-error@+1 {{'svminnm_bf16_x2' needs target feature sme2,sve-b16b16}}
46+
// expected-error@+1 {{'svminnm_bf16_x2' needs target feature sme,sme2,sve-b16b16}}
4747
svminnm_bf16_x2(bf16x2, bf16x2);
48-
// expected-error@+1 {{'svminnm_bf16_x4' needs target feature sme2,sve-b16b16}}
48+
// expected-error@+1 {{'svminnm_bf16_x4' needs target feature sme,sme2,sve-b16b16}}
4949
svminnm_bf16_x4(bf16x4, bf16x4);
50-
}
50+
}

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -14,54 +14,54 @@ void test_features_f16f16(uint32_t slice,
1414
svbfloat16x4_t bzn4, svbfloat16x4_t bzm4)
1515

1616
__arm_streaming __arm_inout("za") {
17-
// expected-error@+1 {{'svmla_single_za16_f16_vg1x2' needs target feature sme-f16f16}}
17+
// expected-error@+1 {{'svmla_single_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
1818
svmla_single_za16_f16_vg1x2(slice, zn2, zm);
19-
// expected-error@+1 {{'svmla_single_za16_f16_vg1x4' needs target feature sme-f16f16}}
19+
// expected-error@+1 {{'svmla_single_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
2020
svmla_single_za16_f16_vg1x4(slice, zn4, zm);
21-
// expected-error@+1 {{'svmls_single_za16_f16_vg1x2' needs target feature sme-f16f16}}
21+
// expected-error@+1 {{'svmls_single_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
2222
svmls_single_za16_f16_vg1x2(slice, zn2, zm);
23-
// expected-error@+1 {{'svmls_single_za16_f16_vg1x4' needs target feature sme-f16f16}}
23+
// expected-error@+1 {{'svmls_single_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
2424
svmls_single_za16_f16_vg1x4(slice, zn4, zm);
25-
// expected-error@+1 {{'svmla_za16_f16_vg1x2' needs target feature sme-f16f16}}
25+
// expected-error@+1 {{'svmla_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
2626
svmla_za16_f16_vg1x2(slice, zn2, zm2);
27-
// expected-error@+1 {{'svmla_za16_f16_vg1x4' needs target feature sme-f16f16}}
27+
// expected-error@+1 {{'svmla_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
2828
svmla_za16_f16_vg1x4(slice, zn4, zm4);
29-
// expected-error@+1 {{'svmls_za16_f16_vg1x2' needs target feature sme-f16f16}}
29+
// expected-error@+1 {{'svmls_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
3030
svmls_za16_f16_vg1x2(slice, zn2, zm2);
31-
// expected-error@+1 {{'svmls_za16_f16_vg1x4' needs target feature sme-f16f16}}
31+
// expected-error@+1 {{'svmls_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
3232
svmls_za16_f16_vg1x4(slice, zn4, zm4);
33-
// expected-error@+1 {{'svmla_lane_za16_f16_vg1x2' needs target feature sme-f16f16}}
33+
// expected-error@+1 {{'svmla_lane_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
3434
svmla_lane_za16_f16_vg1x2(slice, zn2, zm, 7);
35-
// expected-error@+1 {{'svmla_lane_za16_f16_vg1x4' needs target feature sme-f16f16}}
35+
// expected-error@+1 {{'svmla_lane_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
3636
svmla_lane_za16_f16_vg1x4(slice, zn4, zm, 7);
37-
// expected-error@+1 {{'svmls_lane_za16_f16_vg1x2' needs target feature sme-f16f16}}
37+
// expected-error@+1 {{'svmls_lane_za16_f16_vg1x2' needs target feature sme,sme-f16f16}}
3838
svmls_lane_za16_f16_vg1x2(slice, zn2, zm, 7);
39-
// expected-error@+1 {{'svmls_lane_za16_f16_vg1x4' needs target feature sme-f16f16}}
39+
// expected-error@+1 {{'svmls_lane_za16_f16_vg1x4' needs target feature sme,sme-f16f16}}
4040
svmls_lane_za16_f16_vg1x4(slice, zn4, zm, 7);
4141

42-
// expected-error@+1 {{'svmla_single_za16_bf16_vg1x2' needs target feature sme-b16b16}}
42+
// expected-error@+1 {{'svmla_single_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
4343
svmla_single_za16_bf16_vg1x2(slice, bzn2, bzm);
44-
// expected-error@+1 {{'svmla_single_za16_bf16_vg1x4' needs target feature sme-b16b16}}
44+
// expected-error@+1 {{'svmla_single_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
4545
svmla_single_za16_bf16_vg1x4(slice, bzn4, bzm);
46-
// expected-error@+1 {{'svmls_single_za16_bf16_vg1x2' needs target feature sme-b16b16}}
46+
// expected-error@+1 {{'svmls_single_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
4747
svmls_single_za16_bf16_vg1x2(slice, bzn2, bzm);
48-
// expected-error@+1 {{'svmls_single_za16_bf16_vg1x4' needs target feature sme-b16b16}}
48+
// expected-error@+1 {{'svmls_single_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
4949
svmls_single_za16_bf16_vg1x4(slice, bzn4, bzm);
50-
// expected-error@+1 {{'svmla_za16_bf16_vg1x2' needs target feature sme-b16b16}}
50+
// expected-error@+1 {{'svmla_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
5151
svmla_za16_bf16_vg1x2(slice, bzn2, bzm2);
52-
// expected-error@+1 {{'svmla_za16_bf16_vg1x4' needs target feature sme-b16b16}}
52+
// expected-error@+1 {{'svmla_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
5353
svmla_za16_bf16_vg1x4(slice, bzn4, bzm4);
54-
// expected-error@+1 {{'svmls_za16_bf16_vg1x2' needs target feature sme-b16b16}}
54+
// expected-error@+1 {{'svmls_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
5555
svmls_za16_bf16_vg1x2(slice, bzn2, bzm2);
56-
// expected-error@+1 {{'svmls_za16_bf16_vg1x4' needs target feature sme-b16b16}}
56+
// expected-error@+1 {{'svmls_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
5757
svmls_za16_bf16_vg1x4(slice, bzn4, bzm4);
58-
// expected-error@+1 {{'svmla_lane_za16_bf16_vg1x2' needs target feature sme-b16b16}}
58+
// expected-error@+1 {{'svmla_lane_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
5959
svmla_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7);
60-
// expected-error@+1 {{'svmla_lane_za16_bf16_vg1x4' needs target feature sme-b16b16}}
60+
// expected-error@+1 {{'svmla_lane_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
6161
svmla_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7);
62-
// expected-error@+1 {{'svmls_lane_za16_bf16_vg1x2' needs target feature sme-b16b16}}
62+
// expected-error@+1 {{'svmls_lane_za16_bf16_vg1x2' needs target feature sme,sme-b16b16}}
6363
svmls_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7);
64-
// expected-error@+1 {{'svmls_lane_za16_bf16_vg1x4' needs target feature sme-b16b16}}
64+
// expected-error@+1 {{'svmls_lane_za16_bf16_vg1x4' needs target feature sme,sme-b16b16}}
6565
svmls_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7);
6666
}
6767

‎clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@ void test_features(svbool_t pn, svbool_t pm,
88
svfloat16_t zn, svfloat16_t zm,
99
svbfloat16_t znb, svbfloat16_t zmb)
1010
__arm_streaming __arm_inout("za") {
11-
// expected-error@+1 {{'svmopa_za16_bf16_m' needs target feature sme-b16b16}}
11+
// expected-error@+1 {{'svmopa_za16_bf16_m' needs target feature sme,sme-b16b16}}
1212
svmopa_za16_bf16_m(0, pn, pm, znb, zmb);
13-
// expected-error@+1 {{'svmops_za16_bf16_m' needs target feature sme-b16b16}}
13+
// expected-error@+1 {{'svmops_za16_bf16_m' needs target feature sme,sme-b16b16}}
1414
svmops_za16_bf16_m(0, pn, pm, znb, zmb);
15-
// expected-error@+1 {{'svmopa_za16_f16_m' needs target feature sme-f16f16}}
15+
// expected-error@+1 {{'svmopa_za16_f16_m' needs target feature sme,sme-f16f16}}
1616
svmopa_za16_f16_m(0, pn, pm, zn, zm);
17-
// expected-error@+1 {{'svmops_za16_f16_m' needs target feature sme-f16f16}}
17+
// expected-error@+1 {{'svmops_za16_f16_m' needs target feature sme,sme-f16f16}}
1818
svmops_za16_f16_m(0, pn, pm, zn, zm);
1919
}
2020

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