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[AArch64] Remove duplicate code (NFC)
Remove multiple versions of the predicate that checks if the instruction operand is shifted by up to 4.
1 parent 1c241bb commit 4a5b5bf

8 files changed

+75
-97
lines changed

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -671,7 +671,6 @@ include "AArch64Schedule.td"
671671
include "AArch64InstrInfo.td"
672672
include "AArch64SchedPredicates.td"
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include "AArch64SchedPredExynos.td"
674-
include "AArch64SchedPredAmpere.td"
675674
include "AArch64SchedPredNeoverse.td"
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include "AArch64Combine.td"
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‎llvm/lib/Target/AArch64/AArch64SchedAmpere1.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -571,12 +571,12 @@ def Ampere1Write_62cyc_1XY : SchedWriteRes<[Ampere1UnitXY]> {
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// across Unit A or B for both uops.
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def Ampere1Write_Arith : SchedWriteVariant<[
573573
SchedVar<RegExtendedPred, [Ampere1Write_2cyc_2AB]>,
574-
SchedVar<AmpereCheapLSL, [Ampere1Write_1cyc_1AB]>,
574+
SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1AB]>,
575575
SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1AB]>]>;
576576

577577
def Ampere1Write_ArithFlagsetting : SchedWriteVariant<[
578578
SchedVar<RegExtendedPred, [Ampere1Write_2cyc_1AB_1A]>,
579-
SchedVar<AmpereCheapLSL, [Ampere1Write_1cyc_1A]>,
579+
SchedVar<IsCheapLSL, [Ampere1Write_1cyc_1A]>,
580580
SchedVar<NoSchedPred, [Ampere1Write_2cyc_1B_1A]>]>;
581581

582582
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -309,8 +309,8 @@ def : SchedAlias<WriteIEReg, N1Write_2c_1M>;
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// Arithmetic, flagset, LSL shift, shift <= 4
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// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
311311
def N1WriteISReg : SchedWriteVariant<[
312-
SchedVar<NeoverseCheapLSL, [N1Write_1c_1I]>,
313-
SchedVar<NoSchedPred, [N1Write_2c_1M]>]>;
312+
SchedVar<IsCheapLSL, [N1Write_1c_1I]>,
313+
SchedVar<NoSchedPred, [N1Write_2c_1M]>]>;
314314
def : SchedAlias<WriteISReg, N1WriteISReg>;
315315

316316
// Logical, shift, no flagset

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -612,8 +612,8 @@ def N2Write_11cyc_9L01_9S_9V : SchedWriteRes<[N2UnitL01, N2UnitL01, N2UnitL01,
612612
//===----------------------------------------------------------------------===//
613613
// Define types for arithmetic and logical ops with short shifts
614614
def N2Write_Arith : SchedWriteVariant<[
615-
SchedVar<NeoverseCheapLSL, [N2Write_1cyc_1I]>,
616-
SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
615+
SchedVar<IsCheapLSL, [N2Write_1cyc_1I]>,
616+
SchedVar<NoSchedPred, [N2Write_2cyc_1M]>]>;
617617

618618
def N2Write_Logical: SchedWriteVariant<[
619619
SchedVar<NeoverseNoLSL, [N2Write_1cyc_1I]>,

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -877,12 +877,12 @@ def V2Write_11cyc_18L01_18S_18V01 : SchedWriteRes<[V2UnitL01, V2UnitL01,
877877
// Define predicate-controlled types
878878

879879
def V2Write_ArithI : SchedWriteVariant<[
880-
SchedVar<NeoverseCheapLSL, [V2Write_1cyc_1I]>,
881-
SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
880+
SchedVar<IsCheapLSL, [V2Write_1cyc_1I]>,
881+
SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
882882

883883
def V2Write_ArithF : SchedWriteVariant<[
884-
SchedVar<NeoverseCheapLSL, [V2Write_1cyc_1F]>,
885-
SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
884+
SchedVar<IsCheapLSL, [V2Write_1cyc_1F]>,
885+
SchedVar<NoSchedPred, [V2Write_2cyc_1M]>]>;
886886

887887
def V2Write_Logical : SchedWriteVariant<[
888888
SchedVar<NeoverseNoLSL, [V2Write_1cyc_1F]>,

‎llvm/lib/Target/AArch64/AArch64SchedPredAmpere.td

Lines changed: 0 additions & 25 deletions
This file was deleted.

‎llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,17 +13,6 @@
1313

1414
// Auxiliary predicates.
1515

16-
// Check for LSL shift <= 4
17-
def NeoverseCheapLSL : MCSchedPredicate<
18-
CheckAll<
19-
[CheckShiftLSL,
20-
CheckAny<
21-
[CheckShiftBy0,
22-
CheckShiftBy1,
23-
CheckShiftBy2,
24-
CheckShiftBy3,
25-
CheckShiftBy4]>]>>;
26-
2716
// Check for LSL shift == 0
2817
def NeoverseNoLSL : MCSchedPredicate<
2918
CheckAll<[CheckShiftLSL,

‎llvm/lib/Target/AArch64/AArch64SchedPredicates.td

Lines changed: 65 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,12 @@ foreach I = {0-3} in {
3131
def CheckExtBy#I : CheckImmOperand<3, I>;
3232
}
3333

34+
// Check for shifting in arithmetic and logic instructions.
35+
foreach I = {0-4, 8} in {
36+
let FunctionMapper = "AArch64_AM::getShiftValue" in
37+
def CheckShiftBy#I : CheckImmOperand<3, I>;
38+
}
39+
3440
// Check the extension type in the register offset addressing mode.
3541
let FunctionMapper = "AArch64_AM::getMemExtendType" in {
3642
def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
@@ -52,12 +58,6 @@ let FunctionMapper = "AArch64_AM::getShiftType" in {
5258
def CheckShiftMSL : CheckImmOperand_s<3, "AArch64_AM::MSL">;
5359
}
5460

55-
// Check for shifting in arithmetic and logic instructions.
56-
foreach I = {0-4, 8} in {
57-
let FunctionMapper = "AArch64_AM::getShiftValue" in
58-
def CheckShiftBy#I : CheckImmOperand<3, I>;
59-
}
60-
6161
// Generic predicates.
6262
// Identify whether an instruction is NEON or floating point
6363
def CheckFpOrNEON : CheckFunctionPredicateWithTII<
@@ -218,38 +218,6 @@ def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpco
218218

219219
// Target predicates.
220220

221-
// Identify an instruction that effectively transfers a register to another.
222-
def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
223-
MCOpcodeSwitchStatement<
224-
[// MOV {Rd, SP}, {SP, Rn} =>
225-
// ADD {Rd, SP}, {SP, Rn}, #0
226-
MCOpcodeSwitchCase<
227-
[ADDWri, ADDXri],
228-
MCReturnStatement<
229-
CheckAll<
230-
[CheckIsRegOperand<0>,
231-
CheckIsRegOperand<1>,
232-
CheckAny<
233-
[CheckRegOperand<0, WSP>,
234-
CheckRegOperand<0, SP>,
235-
CheckRegOperand<1, WSP>,
236-
CheckRegOperand<1, SP>]>,
237-
CheckZeroOperand<2>]>>>,
238-
// MOV Rd, Rm =>
239-
// ORR Rd, ZR, Rm, LSL #0
240-
MCOpcodeSwitchCase<
241-
[ORRWrs, ORRXrs],
242-
MCReturnStatement<
243-
CheckAll<
244-
[CheckIsRegOperand<1>,
245-
CheckIsRegOperand<2>,
246-
CheckAny<
247-
[CheckRegOperand<1, WZR>,
248-
CheckRegOperand<1, XZR>]>,
249-
CheckShiftBy0]>>>],
250-
MCReturnStatement<FalsePred>>>;
251-
def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
252-
253221
// Identify arithmetic instructions with an extended register.
254222
def RegExtendedFn : TIIPredicate<"hasExtendedReg",
255223
MCOpcodeSwitchStatement<
@@ -282,24 +250,52 @@ def ScaledIdxFn : TIIPredicate<"isScaledAddr",
282250
MCReturnStatement<FalsePred>>>;
283251
def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
284252

285-
// Identify an instruction that effectively resets a FP register to zero.
286-
def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
253+
// Special cases.
254+
255+
// Check for LSL shift <= 4
256+
def IsCheapLSL : MCSchedPredicate<
257+
CheckAll<
258+
[CheckShiftLSL,
259+
CheckAny<
260+
[CheckShiftBy0,
261+
CheckShiftBy1,
262+
CheckShiftBy2,
263+
CheckShiftBy3,
264+
CheckShiftBy4]>]>>;
265+
266+
// Idioms.
267+
268+
// Identify an instruction that effectively transfers a register to another.
269+
def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
287270
MCOpcodeSwitchStatement<
288-
[// MOVI Vd, #0
271+
[// MOV {Rd, SP}, {SP, Rn} =>
272+
// ADD {Rd, SP}, {SP, Rn}, #0
289273
MCOpcodeSwitchCase<
290-
[MOVIv8b_ns, MOVIv16b_ns,
291-
MOVID, MOVIv2d_ns],
292-
MCReturnStatement<CheckZeroOperand<1>>>,
293-
// MOVI Vd, #0, LSL #0
274+
[ADDWri, ADDXri],
275+
MCReturnStatement<
276+
CheckAll<
277+
[CheckIsRegOperand<0>,
278+
CheckIsRegOperand<1>,
279+
CheckAny<
280+
[CheckRegOperand<0, WSP>,
281+
CheckRegOperand<0, SP>,
282+
CheckRegOperand<1, WSP>,
283+
CheckRegOperand<1, SP>]>,
284+
CheckZeroOperand<2>]>>>,
285+
// MOV Rd, Rm =>
286+
// ORR Rd, ZR, Rm, LSL #0
294287
MCOpcodeSwitchCase<
295-
[MOVIv4i16, MOVIv8i16,
296-
MOVIv2i32, MOVIv4i32],
288+
[ORRWrs, ORRXrs],
297289
MCReturnStatement<
298290
CheckAll<
299-
[CheckZeroOperand<1>,
300-
CheckZeroOperand<2>]>>>],
291+
[CheckIsRegOperand<1>,
292+
CheckIsRegOperand<2>,
293+
CheckAny<
294+
[CheckRegOperand<1, WZR>,
295+
CheckRegOperand<1, XZR>]>,
296+
CheckShiftBy0]>>>],
301297
MCReturnStatement<FalsePred>>>;
302-
def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
298+
def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
303299

304300
// Identify an instruction that effectively resets a GP register to zero.
305301
def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
@@ -317,6 +313,25 @@ def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
317313
MCReturnStatement<FalsePred>>>;
318314
def IsZeroIdiomPred : MCSchedPredicate<IsZeroIdiomFn>;
319315

316+
// Identify an instruction that effectively resets a FP register to zero.
317+
def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
318+
MCOpcodeSwitchStatement<
319+
[// MOVI Vd, #0
320+
MCOpcodeSwitchCase<
321+
[MOVIv8b_ns, MOVIv16b_ns,
322+
MOVID, MOVIv2d_ns],
323+
MCReturnStatement<CheckZeroOperand<1>>>,
324+
// MOVI Vd, #0, LSL #0
325+
MCOpcodeSwitchCase<
326+
[MOVIv4i16, MOVIv8i16,
327+
MOVIv2i32, MOVIv4i32],
328+
MCReturnStatement<
329+
CheckAll<
330+
[CheckZeroOperand<1>,
331+
CheckZeroOperand<2>]>>>],
332+
MCReturnStatement<FalsePred>>>;
333+
def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
334+
320335
// Identify EXTR as the alias for ROR (immediate).
321336
def IsRORImmIdiomPred : MCSchedPredicate<
322337
CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,

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