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michaelmaitlandmichaelmaitland
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fixup! update regbank tests
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+250
-149
lines changed

3 files changed

+250
-149
lines changed

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv32.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck %s
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---
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name: splat_zero_nxv1i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv1i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv2i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv2i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 2 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv4i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv4i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 4 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv8i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv8i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 8 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv16i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv16i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 16 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv32i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv32i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 32 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv64i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv64i1
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; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s32) = G_CONSTANT i32 -1
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%1:_(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
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$v0 = COPY %1(<vscale x 64 x s1>)
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PseudoRET implicit $v0
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...
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‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr-rv64.mir

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck %s
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---
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name: splat_zero_nxv1i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv1i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 1 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv2i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv2i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 2 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv4i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv4i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 4 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv8i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv8i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 8 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv16i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv16i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 16 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv32i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv32i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 32 x s1>)
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PseudoRET implicit $v0
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...
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---
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name: splat_zero_nxv64i1
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legalized: true
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regBankSelected: false
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body: |
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bb.1:
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; CHECK-LABEL: name: splat_zero_nxv64i1
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; CHECK: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 -1
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; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s64)
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; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
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; CHECK-NEXT: PseudoRET implicit $v0
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%0:_(s64) = G_CONSTANT i64 -1
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%1:_(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
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$v0 = COPY %1(<vscale x 64 x s1>)
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PseudoRET implicit $v0
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...
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