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[AArch64] Add SVE lowering of fixed-length UABD/SABD (#104991)
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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@@ -2055,6 +2055,8 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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bool PreferSVE = !PreferNEON && Subtarget->isSVEAvailable();
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// Lower fixed length vector operations to scalable equivalents.
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setOperationAction(ISD::ABDS, VT, Default);
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setOperationAction(ISD::ABDU, VT, Default);
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setOperationAction(ISD::ABS, VT, Default);
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setOperationAction(ISD::ADD, VT, Default);
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setOperationAction(ISD::AND, VT, Default);

‎llvm/test/CodeGen/AArch64/sve-fixed-length-int-abd.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE for 128-bit vectors.
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define void @sabd_v16i8_v16i16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v16i8_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <16 x i8>, ptr %a
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%b.ld = load <16 x i8>, ptr %b
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%a.sext = sext <16 x i8> %a.ld to <16 x i16>
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%b.sext = sext <16 x i8> %b.ld to <16 x i16>
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%sub = sub <16 x i16> %a.sext, %b.sext
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%abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 true)
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%trunc = trunc <16 x i16> %abs to <16 x i8>
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store <16 x i8> %trunc, ptr %a
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ret void
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}
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; Don't use SVE for 128-bit vectors.
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define void @sabd_v16i8_v16i32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v16i8_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <16 x i8>, ptr %a
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%b.ld = load <16 x i8>, ptr %b
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%a.sext = sext <16 x i8> %a.ld to <16 x i32>
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%b.sext = sext <16 x i8> %b.ld to <16 x i32>
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%sub = sub <16 x i32> %a.sext, %b.sext
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%abs = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %sub, i1 true)
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%trunc = trunc <16 x i32> %abs to <16 x i8>
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store <16 x i8> %trunc, ptr %a
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ret void
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}
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; Don't use SVE for 128-bit vectors.
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define void @sabd_v16i8_v16i64(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v16i8_v16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sabd v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <16 x i8>, ptr %a
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%b.ld = load <16 x i8>, ptr %b
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%a.sext = sext <16 x i8> %a.ld to <16 x i64>
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%b.sext = sext <16 x i8> %b.ld to <16 x i64>
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%sub = sub <16 x i64> %a.sext, %b.sext
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%abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 true)
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%trunc = trunc <16 x i64> %abs to <16 x i8>
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store <16 x i8> %trunc, ptr %a
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ret void
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}
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define void @sabd_v32i8_v32i16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v32i8_v32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
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; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <32 x i8>, ptr %a
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%b.ld = load <32 x i8>, ptr %b
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%a.sext = sext <32 x i8> %a.ld to <32 x i16>
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%b.sext = sext <32 x i8> %b.ld to <32 x i16>
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%sub = sub <32 x i16> %a.sext, %b.sext
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%abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)
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%trunc = trunc <32 x i16> %abs to <32 x i8>
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store <32 x i8> %trunc, ptr %a
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ret void
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}
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define void @uabd_v32i8_v32i16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: uabd_v32i8_v32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
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; CHECK-NEXT: uabd z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <32 x i8>, ptr %a
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%b.ld = load <32 x i8>, ptr %b
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%a.zext = zext <32 x i8> %a.ld to <32 x i16>
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%b.zext = zext <32 x i8> %b.ld to <32 x i16>
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%sub = sub <32 x i16> %a.zext, %b.zext
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%abs = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %sub, i1 true)
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%trunc = trunc <32 x i16> %abs to <32 x i8>
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store <32 x i8> %trunc, ptr %a
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ret void
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}
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define void @sabd_v32i8_v32i32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v32i8_v32i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
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; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <32 x i8>, ptr %a
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%b.ld = load <32 x i8>, ptr %b
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%a.sext = sext <32 x i8> %a.ld to <32 x i32>
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%b.sext = sext <32 x i8> %b.ld to <32 x i32>
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%sub = sub <32 x i32> %a.sext, %b.sext
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%abs = call <32 x i32> @llvm.abs.v32i32(<32 x i32> %sub, i1 true)
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%trunc = trunc <32 x i32> %abs to <32 x i8>
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store <32 x i8> %trunc, ptr %a
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ret void
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}
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define void @sabd_v32i8_v32i64(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: sabd_v32i8_v32i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
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; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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%a.ld = load <32 x i8>, ptr %a
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%b.ld = load <32 x i8>, ptr %b
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%a.sext = sext <32 x i8> %a.ld to <32 x i64>
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%b.sext = sext <32 x i8> %b.ld to <32 x i64>
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%sub = sub <32 x i64> %a.sext, %b.sext
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%abs = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %sub, i1 true)
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%trunc = trunc <32 x i64> %abs to <32 x i8>
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store <32 x i8> %trunc, ptr %a
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ret void
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}
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define void @sabd_v64i8_v64i64(ptr %a, ptr %b) #0 {
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; VBITS_GE_256-LABEL: sabd_v64i8_v64i64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.b, vl32
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; VBITS_GE_256-NEXT: mov w8, #32 // =0x20
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; VBITS_GE_256-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
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; VBITS_GE_256-NEXT: ld1b { z1.b }, p0/z, [x1, x8]
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; VBITS_GE_256-NEXT: ld1b { z2.b }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1b { z3.b }, p0/z, [x1]
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; VBITS_GE_256-NEXT: sabd z0.b, p0/m, z0.b, z1.b
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; VBITS_GE_256-NEXT: movprfx z1, z2
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; VBITS_GE_256-NEXT: sabd z1.b, p0/m, z1.b, z3.b
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; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0, x8]
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; VBITS_GE_256-NEXT: st1b { z1.b }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: sabd_v64i8_v64i64:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.b, vl64
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; VBITS_GE_512-NEXT: ld1b { z0.b }, p0/z, [x0]
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; VBITS_GE_512-NEXT: ld1b { z1.b }, p0/z, [x1]
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; VBITS_GE_512-NEXT: sabd z0.b, p0/m, z0.b, z1.b
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; VBITS_GE_512-NEXT: st1b { z0.b }, p0, [x0]
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; VBITS_GE_512-NEXT: ret
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%a.ld = load <64 x i8>, ptr %a
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%b.ld = load <64 x i8>, ptr %b
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%a.sext = sext <64 x i8> %a.ld to <64 x i64>
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%b.sext = sext <64 x i8> %b.ld to <64 x i64>
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%sub = sub <64 x i64> %a.sext, %b.sext
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%abs = call <64 x i64> @llvm.abs.v64i64(<64 x i64> %sub, i1 true)
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%trunc = trunc <64 x i64> %abs to <64 x i8>
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store <64 x i8> %trunc, ptr %a
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ret void
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}
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attributes #0 = { "target-features"="+neon,+sve" }

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