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kosarevkosarev
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[AMDGPU][AsmParser][NFC] Rename integer modifier operands to follow the convention. (#79284)
Part of <#62629>.
1 parent 2aa8945 commit 4b8e55c

10 files changed

+102
-102
lines changed

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
163163
(ins SCSrc_b32:$soffset));
164164

165165
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset,
166-
(ins offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
166+
(ins Offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
167167

168168
dag Inputs = !if(!empty(vaddrList),
169169
NonVaddrInputs,
@@ -410,7 +410,7 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
410410
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdataClass, isTFE>.ret;
411411

412412
dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
413-
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
413+
dag NonVaddrInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
414414

415415
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
416416
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
@@ -664,7 +664,7 @@ multiclass MUBUF_Pseudo_Stores<string opName, ValueType store_vt = i32> {
664664
class MUBUF_Pseudo_Store_Lds<string opName>
665665
: MUBUF_Pseudo<opName,
666666
(outs),
667-
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, i1imm:$swz),
667+
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
668668
" $srsrc, $soffset$offset lds$cpol"> {
669669
let LGKM_CNT = 1;
670670
let mayLoad = 1;
@@ -687,7 +687,7 @@ class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in, bit hasGFX12En
687687
dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
688688
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
689689
dag SOffset = !if(hasGFX12Enc, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
690-
dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins offset:$offset));
690+
dag MainInputs = !con((ins SReg_128:$srsrc), SOffset, (ins Offset:$offset));
691691
dag CPol = !if(vdata_in, (ins CPol_GLC_WithDefault:$cpol),
692692
(ins CPol_NonGLC_WithDefault:$cpol));
693693

@@ -1537,14 +1537,14 @@ multiclass BufferAtomicPat_Common<string OpPrefix, ValueType vt, string Inst, bi
15371537
def : GCNPat<
15381538
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), vt:$vdata_in)),
15391539
(!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix) getVregSrcForVT<vt>.ret:$vdata_in,
1540-
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset)
1540+
SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset)
15411541
>;
15421542

15431543
def : GCNPat<
15441544
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
15451545
vt:$vdata_in)),
15461546
(!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix) getVregSrcForVT<vt>.ret:$vdata_in,
1547-
VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset)
1547+
VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset, Offset:$offset)
15481548
>;
15491549
} // end let AddedComplexity
15501550

@@ -1574,7 +1574,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15741574
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
15751575
defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
15761576
data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
1577-
offset:$offset);
1577+
Offset:$offset);
15781578
def : GCNPat<
15791579
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)),
15801580
!if(!eq(RtnMode, "ret"),
@@ -1585,7 +1585,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15851585

15861586
defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
15871587
data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
1588-
SCSrc_b32:$soffset, offset:$offset);
1588+
SCSrc_b32:$soffset, Offset:$offset);
15891589
def : GCNPat<
15901590
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
15911591
data_vt:$vdata_in)),

‎llvm/lib/Target/AMDGPU/DSDIRInstructions.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -52,16 +52,16 @@ class VDSDIRe<bits<2> op, bit is_direct> : Enc32 {
5252

5353
class LDSDIR_getIns<bit direct> {
5454
dag ret = !if(direct,
55-
(ins wait_vdst:$waitvdst),
56-
(ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_vdst:$waitvdst)
55+
(ins WaitVDST:$waitvdst),
56+
(ins InterpAttr:$attr, InterpAttrChan:$attrchan, WaitVDST:$waitvdst)
5757
);
5858
}
5959

6060
class VDSDIR_getIns<bit direct> {
6161
dag ret = !if(direct,
62-
(ins wait_va_vdst:$waitvdst, wait_va_vsrc:$waitvsrc),
63-
(ins InterpAttr:$attr, InterpAttrChan:$attrchan, wait_va_vdst:$waitvdst,
64-
wait_va_vsrc:$waitvsrc)
62+
(ins WaitVAVDst:$waitvdst, WaitVMVSrc:$waitvsrc),
63+
(ins InterpAttr:$attr, InterpAttrChan:$attrchan, WaitVAVDst:$waitvdst,
64+
WaitVMVSrc:$waitvsrc)
6565
);
6666
}
6767

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
9595
class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
9696
: DS_Pseudo<opName,
9797
(outs),
98-
(ins getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
98+
(ins getLdStRegisterOperand<rc>.ret:$data0, Offset:$offset, gds:$gds),
9999
" $data0$offset$gds"> {
100100

101101
let has_addr = 0;
@@ -106,7 +106,7 @@ class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
106106
class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
107107
: DS_Pseudo<opName,
108108
(outs),
109-
(ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
109+
(ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, Offset:$offset, gds:$gds),
110110
" $addr, $data0$offset$gds"> {
111111

112112
let has_data1 = 0;
@@ -135,7 +135,7 @@ class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
135135
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
136136
: DS_Pseudo<opName,
137137
(outs),
138-
(ins VGPR_32:$addr, data_op:$data0, data_op:$data1, offset:$offset, gds:$gds),
138+
(ins VGPR_32:$addr, data_op:$data0, data_op:$data1, Offset:$offset, gds:$gds),
139139
" $addr, $data0, $data1$offset$gds"> {
140140

141141
let has_vdst = 0;
@@ -157,7 +157,7 @@ class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
157157
: DS_Pseudo<opName,
158158
(outs),
159159
(ins VGPR_32:$addr, data_op:$data0, data_op:$data1,
160-
offset0:$offset0, offset1:$offset1, gds:$gds),
160+
Offset0:$offset0, Offset1:$offset1, gds:$gds),
161161
" $addr, $data0, $data1$offset0$offset1$gds"> {
162162

163163
let has_vdst = 0;
@@ -177,7 +177,7 @@ class DS_0A1D_RET_GDS<string opName, RegisterClass rc = VGPR_32, RegisterClass s
177177
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
178178
: DS_Pseudo<opName,
179179
(outs dst_op:$vdst),
180-
(ins src_op:$data0, offset:$offset),
180+
(ins src_op:$data0, Offset:$offset),
181181
" $vdst, $data0$offset gds"> {
182182

183183
let has_addr = 0;
@@ -191,7 +191,7 @@ class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
191191
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
192192
: DS_Pseudo<opName,
193193
(outs data_op:$vdst),
194-
(ins VGPR_32:$addr, data_op:$data0, offset:$offset, gds:$gds),
194+
(ins VGPR_32:$addr, data_op:$data0, Offset:$offset, gds:$gds),
195195
" $vdst, $addr, $data0$offset$gds"> {
196196

197197
let hasPostISelHook = 1;
@@ -227,7 +227,7 @@ class DS_1A2D_RET<string opName,
227227
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
228228
: DS_Pseudo<opName,
229229
(outs dst_op:$vdst),
230-
(ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset:$offset, gds:$gds),
230+
(ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset:$offset, gds:$gds),
231231
" $vdst, $addr, $data0, $data1$offset$gds"> {
232232

233233
let hasPostISelHook = 1;
@@ -254,7 +254,7 @@ class DS_1A2D_Off8_RET<string opName,
254254
RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
255255
: DS_Pseudo<opName,
256256
(outs dst_op:$vdst),
257-
(ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
257+
(ins VGPR_32:$addr, src_op:$data0, src_op:$data1, Offset0:$offset0, Offset1:$offset1, gds:$gds),
258258
" $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
259259

260260
let has_offset = 0;
@@ -274,7 +274,7 @@ multiclass DS_1A2D_Off8_RET_mc<string opName,
274274
class DS_BVH_STACK<string opName>
275275
: DS_Pseudo<opName,
276276
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst, VGPR_32:$addr),
277-
(ins VGPR_32:$addr_in, getLdStRegisterOperand<VGPR_32>.ret:$data0, VReg_128:$data1, offset:$offset),
277+
(ins VGPR_32:$addr_in, getLdStRegisterOperand<VGPR_32>.ret:$data0, VReg_128:$data1, Offset:$offset),
278278
" $vdst, $addr, $data0, $data1$offset"> {
279279
let Constraints = "$addr = $addr_in";
280280
let DisableEncoding = "$addr_in";
@@ -285,7 +285,7 @@ class DS_BVH_STACK<string opName>
285285
let SchedRW = [WriteLDS, WriteLDS];
286286
}
287287

288-
class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset,
288+
class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = Offset,
289289
RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
290290
: DS_Pseudo<opName,
291291
(outs data_op:$vdst),
@@ -299,7 +299,7 @@ class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0
299299
let has_data1 = 0;
300300
}
301301

302-
multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
302+
multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = Offset> {
303303
def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
304304

305305
let has_m0_read = 0 in {
@@ -313,7 +313,7 @@ class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
313313
class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
314314
: DS_Pseudo<opName,
315315
(outs getLdStRegisterOperand<rc>.ret:$vdst),
316-
(ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
316+
(ins VGPR_32:$addr, Offset0:$offset0, Offset1:$offset1, gds:$gds),
317317
" $vdst, $addr$offset0$offset1$gds"> {
318318

319319
let has_offset = 0;
@@ -331,7 +331,7 @@ multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
331331

332332
class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
333333
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
334-
(ins VGPR_32:$addr, offset:$offset),
334+
(ins VGPR_32:$addr, Offset:$offset),
335335
" $vdst, $addr$offset gds"> {
336336

337337
let has_data0 = 0;
@@ -342,7 +342,7 @@ class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
342342

343343
class DS_0A_RET <string opName> : DS_Pseudo<opName,
344344
(outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
345-
(ins offset:$offset, gds:$gds),
345+
(ins Offset:$offset, gds:$gds),
346346
" $vdst$offset$gds"> {
347347

348348
let mayLoad = 1;
@@ -355,7 +355,7 @@ class DS_0A_RET <string opName> : DS_Pseudo<opName,
355355

356356
class DS_1A <string opName> : DS_Pseudo<opName,
357357
(outs),
358-
(ins VGPR_32:$addr, offset:$offset, gds:$gds),
358+
(ins VGPR_32:$addr, Offset:$offset, gds:$gds),
359359
" $addr$offset$gds"> {
360360

361361
let mayLoad = 1;
@@ -390,13 +390,13 @@ class DS_GWS <string opName, dag ins, string asmOps>
390390

391391
class DS_GWS_0D <string opName>
392392
: DS_GWS<opName,
393-
(ins offset:$offset), "$offset gds"> {
393+
(ins Offset:$offset), "$offset gds"> {
394394
let hasSideEffects = 1;
395395
}
396396

397397
class DS_GWS_1D <string opName>
398398
: DS_GWS<opName,
399-
(ins getLdStRegisterOperand<VGPR_32>.ret:$data0, offset:$offset),
399+
(ins getLdStRegisterOperand<VGPR_32>.ret:$data0, Offset:$offset),
400400
" $data0$offset gds"> {
401401

402402
let has_gws_data0 = 1;
@@ -424,7 +424,7 @@ class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
424424
RegisterOperand data_op = getLdStRegisterOperand<VGPR_32>.ret>
425425
: DS_Pseudo<opName,
426426
(outs data_op:$vdst),
427-
(ins VGPR_32:$addr, data_op:$data0, offset:$offset),
427+
(ins VGPR_32:$addr, data_op:$data0, Offset:$offset),
428428
" $vdst, $addr, $data0$offset",
429429
[(set i32:$vdst,
430430
(node (DS1Addr1Offset i32:$addr, i32:$offset), i32:$data0))] > {
@@ -439,7 +439,7 @@ class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
439439

440440
class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, int complexity = 0,
441441
bit gds=0> : GCNPat <(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
442-
(inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))> {
442+
(inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))> {
443443
let AddedComplexity = complexity;
444444
}
445445

@@ -767,7 +767,7 @@ def : GCNPat <
767767

768768
class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
769769
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
770-
(inst $ptr, offset:$offset, (i1 gds))
770+
(inst $ptr, Offset:$offset, (i1 gds))
771771
>;
772772

773773
multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
@@ -783,7 +783,7 @@ multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
783783

784784
class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
785785
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$in),
786-
(inst $ptr, offset:$offset, (i1 0), $in)
786+
(inst $ptr, Offset:$offset, (i1 0), $in)
787787
>;
788788

789789
defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
@@ -827,7 +827,7 @@ def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
827827

828828
class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
829829
(frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
830-
(inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
830+
(inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))
831831
>;
832832

833833
multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
@@ -1022,7 +1022,7 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9GFX10 in {
10221022
class DSAtomicCmpXChgSwapped<DS_Pseudo inst, ValueType vt, PatFrag frag,
10231023
int complexity = 0, bit gds=0> : GCNPat<
10241024
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
1025-
(inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))> {
1025+
(inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, Offset:$offset, (i1 gds))> {
10261026
let AddedComplexity = complexity;
10271027
}
10281028

@@ -1056,7 +1056,7 @@ let SubtargetPredicate = isGFX11Plus in {
10561056
class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag,
10571057
int complexity = 0, bit gds=0> : GCNPat<
10581058
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
1059-
(inst $ptr, getVregSrcForVT<vt>.ret:$swap, getVregSrcForVT<vt>.ret:$cmp, offset:$offset, (i1 gds))> {
1059+
(inst $ptr, getVregSrcForVT<vt>.ret:$swap, getVregSrcForVT<vt>.ret:$cmp, Offset:$offset, (i1 gds))> {
10601060
let AddedComplexity = complexity;
10611061
}
10621062

@@ -1136,7 +1136,7 @@ def : DSAtomicRetPat<DS_ADD_F64, f64, atomic_load_fadd_local_noret_64>;
11361136
class DSAtomicRetPatIntrinsic<DS_Pseudo inst, ValueType vt, PatFrag frag,
11371137
bit gds=0> : GCNPat <
11381138
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value)),
1139-
(inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))> {
1139+
(inst $ptr, getVregSrcForVT<vt>.ret:$value, Offset:$offset, (i1 gds))> {
11401140
}
11411141

11421142
def : DSAtomicRetPatIntrinsic<DS_ADD_RTN_F64, f64, int_amdgcn_flat_atomic_fadd_local_addrspace>;

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