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[PAuthLR] Make CFI Instruction Location Consistent
With the introduction of `.cfi_negate_ra_state_with_pc`, the location of the CFI Instructions are inconsistent, with `.cfi_negate_ra_state_with_pc` needing to be emitted directly after the signing instruction, and `.cfi_negate_ra_state` being emitted with other CFI instructions as part of the prolog. To ensure consistency between the two CFI Instructions, they are now emitted after the CFI Instruction, regardless of which one is being used. This reverses the changes made in #96377, as this is the commit that moved the CFI instructions initially.
1 parent 961092b commit 4bbb760

11 files changed

+370
-127
lines changed

‎llvm/lib/Target/AArch64/AArch64PointerAuth.cpp

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -114,29 +114,11 @@ static void emitPACCFI(const AArch64Subtarget &Subtarget,
114114
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
115115
auto &MF = *MBB.getParent();
116116
auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
117-
bool EmitAsyncCFI = MFnI.needsAsyncDwarfUnwindInfo(MF);
118117

119118
auto CFIInst = MFnI.branchProtectionPAuthLR()
120119
? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
121120
: MCCFIInstruction::createNegateRAState(nullptr);
122121

123-
// Because of PAuthLR, when using NegateRAStateWithPC, the CFI instruction cannot
124-
// be bundled with other CFI instructions in the prolog, as it needs to directly
125-
// follow the signing instruction. This ensures the PC value is captured incase of
126-
// an error in the following the following instructions.
127-
if (!EmitAsyncCFI && !(MFnI.branchProtectionPAuthLR())) {
128-
// Reduce the size of the generated call frame information for synchronous
129-
// CFI by bundling the new CFI instruction with others in the prolog, so
130-
// that no additional DW_CFA_advance_loc is needed.
131-
for (auto I = MBBI; I != MBB.end(); ++I) {
132-
if (I->getOpcode() == TargetOpcode::CFI_INSTRUCTION &&
133-
I->getFlag(MachineInstr::FrameSetup)) {
134-
MBBI = I;
135-
break;
136-
}
137-
}
138-
}
139-
140122
unsigned CFIIndex = MF.addFrameInst(CFIInst);
141123
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
142124
.addCFIIndex(CFIIndex)

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,7 @@ define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" {
1111
; CHECK-NEXT: .cfi_b_key_frame
1212
; V8A-NEXT: hint #27
1313
; V83A-NEXT: pacibsp
14-
; CHECK: .cfi_negate_ra_state
15-
; CHECK-NEXT: .cfi_def_cfa_offset
14+
; CHECK-NEXT: .cfi_negate_ra_state
1615
%1 = alloca i32, align 4
1716
%2 = alloca i32, align 4
1817
%3 = alloca i32, align 4

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,7 @@ define void @a() "sign-return-address"="all" {
77
; CHECK-LABEL: a: // @a
88
; V8A: hint #25
99
; V83A: paciasp
10-
; CHECK: .cfi_negate_ra_state
11-
; CHECK-NEXT: .cfi_def_cfa_offset
10+
; CHECK-NEXT: .cfi_negate_ra_state
1211
%1 = alloca i32, align 4
1312
%2 = alloca i32, align 4
1413
%3 = alloca i32, align 4
@@ -55,8 +54,7 @@ define void @c() "sign-return-address"="all" {
5554
; CHECK-LABEL: c: // @c
5655
; V8A: hint #25
5756
; V83A: paciasp
58-
; CHECK: .cfi_negate_ra_state
59-
; CHECK-NEXT: .cfi_def_cfa_offset
57+
; CHECK-NEXT .cfi_negate_ra_state
6058
%1 = alloca i32, align 4
6159
%2 = alloca i32, align 4
6260
%3 = alloca i32, align 4

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll

Lines changed: 103 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,44 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
23
; RUN: FileCheck %s --check-prefixes CHECK,V8A
34
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
45
; RUN: FileCheck %s --check-prefixes CHECK,V83A
56

67
define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
7-
; CHECK-LABEL: a: // @a
8-
; CHECK: .cfi_b_key_frame
9-
; V8A-NEXT: hint #27
10-
; V83A-NEXT: pacibsp
11-
; CHECK: .cfi_negate_ra_state
12-
; CHECK-NEXT: .cfi_def_cfa_offset
8+
; V8A-LABEL: a:
9+
; V8A: // %bb.0:
10+
; V8A-NEXT: .cfi_b_key_frame
11+
; V8A-NEXT: hint #27
12+
; V8A-NEXT: .cfi_negate_ra_state
13+
; V8A-NEXT: sub sp, sp, #32
14+
; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
15+
; V8A-NEXT: .cfi_def_cfa_offset 32
16+
; V8A-NEXT: .cfi_offset w30, -16
17+
; V8A-NEXT: bl OUTLINED_FUNCTION_0
18+
; V8A-NEXT: //APP
19+
; V8A-NEXT: mov x30, x0
20+
; V8A-NEXT: //NO_APP
21+
; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
22+
; V8A-NEXT: add sp, sp, #32
23+
; V8A-NEXT: hint #31
24+
; V8A-NEXT: ret
25+
;
26+
; V83A-LABEL: a:
27+
; V83A: // %bb.0:
28+
; V83A-NEXT: .cfi_b_key_frame
29+
; V83A-NEXT: pacibsp
30+
; V83A-NEXT: .cfi_negate_ra_state
31+
; V83A-NEXT: sub sp, sp, #32
32+
; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
33+
; V83A-NEXT: .cfi_def_cfa_offset 32
34+
; V83A-NEXT: .cfi_offset w30, -16
35+
; V83A-NEXT: bl OUTLINED_FUNCTION_0
36+
; V83A-NEXT: //APP
37+
; V83A-NEXT: mov x30, x0
38+
; V83A-NEXT: //NO_APP
39+
; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
40+
; V83A-NEXT: add sp, sp, #32
41+
; V83A-NEXT: retab
1342
%1 = alloca i32, align 4
1443
%2 = alloca i32, align 4
1544
%3 = alloca i32, align 4
@@ -27,12 +56,40 @@ define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"
2756
}
2857

2958
define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
30-
; CHECK-LABEL: b: // @b
31-
; CHECK: .cfi_b_key_frame
32-
; V8A-NEXT: hint #27
33-
; V83A-NEXT: pacibsp
34-
; CHECK: .cfi_negate_ra_state
35-
; CHECK-NEXT: .cfi_def_cfa_offset
59+
; V8A-LABEL: b:
60+
; V8A: // %bb.0:
61+
; V8A-NEXT: .cfi_b_key_frame
62+
; V8A-NEXT: hint #27
63+
; V8A-NEXT: .cfi_negate_ra_state
64+
; V8A-NEXT: sub sp, sp, #32
65+
; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
66+
; V8A-NEXT: .cfi_def_cfa_offset 32
67+
; V8A-NEXT: .cfi_offset w30, -16
68+
; V8A-NEXT: bl OUTLINED_FUNCTION_0
69+
; V8A-NEXT: //APP
70+
; V8A-NEXT: mov x30, x0
71+
; V8A-NEXT: //NO_APP
72+
; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
73+
; V8A-NEXT: add sp, sp, #32
74+
; V8A-NEXT: hint #31
75+
; V8A-NEXT: ret
76+
;
77+
; V83A-LABEL: b:
78+
; V83A: // %bb.0:
79+
; V83A-NEXT: .cfi_b_key_frame
80+
; V83A-NEXT: pacibsp
81+
; V83A-NEXT: .cfi_negate_ra_state
82+
; V83A-NEXT: sub sp, sp, #32
83+
; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
84+
; V83A-NEXT: .cfi_def_cfa_offset 32
85+
; V83A-NEXT: .cfi_offset w30, -16
86+
; V83A-NEXT: bl OUTLINED_FUNCTION_0
87+
; V83A-NEXT: //APP
88+
; V83A-NEXT: mov x30, x0
89+
; V83A-NEXT: //NO_APP
90+
; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
91+
; V83A-NEXT: add sp, sp, #32
92+
; V83A-NEXT: retab
3693
%1 = alloca i32, align 4
3794
%2 = alloca i32, align 4
3895
%3 = alloca i32, align 4
@@ -50,12 +107,40 @@ define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"
50107
}
51108

52109
define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
53-
; CHECK-LABEL: c: // @c
54-
; CHECK: .cfi_b_key_frame
55-
; V8A-NEXT: hint #27
56-
; V83A-NEXT: pacibsp
57-
; CHECK: .cfi_negate_ra_state
58-
; CHECK-NEXT: .cfi_def_cfa_offset
110+
; V8A-LABEL: c:
111+
; V8A: // %bb.0:
112+
; V8A-NEXT: .cfi_b_key_frame
113+
; V8A-NEXT: hint #27
114+
; V8A-NEXT: .cfi_negate_ra_state
115+
; V8A-NEXT: sub sp, sp, #32
116+
; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
117+
; V8A-NEXT: .cfi_def_cfa_offset 32
118+
; V8A-NEXT: .cfi_offset w30, -16
119+
; V8A-NEXT: bl OUTLINED_FUNCTION_0
120+
; V8A-NEXT: //APP
121+
; V8A-NEXT: mov x30, x0
122+
; V8A-NEXT: //NO_APP
123+
; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
124+
; V8A-NEXT: add sp, sp, #32
125+
; V8A-NEXT: hint #31
126+
; V8A-NEXT: ret
127+
;
128+
; V83A-LABEL: c:
129+
; V83A: // %bb.0:
130+
; V83A-NEXT: .cfi_b_key_frame
131+
; V83A-NEXT: pacibsp
132+
; V83A-NEXT: .cfi_negate_ra_state
133+
; V83A-NEXT: sub sp, sp, #32
134+
; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
135+
; V83A-NEXT: .cfi_def_cfa_offset 32
136+
; V83A-NEXT: .cfi_offset w30, -16
137+
; V83A-NEXT: bl OUTLINED_FUNCTION_0
138+
; V83A-NEXT: //APP
139+
; V83A-NEXT: mov x30, x0
140+
; V83A-NEXT: //NO_APP
141+
; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
142+
; V83A-NEXT: add sp, sp, #32
143+
; V83A-NEXT: retab
59144
%1 = alloca i32, align 4
60145
%2 = alloca i32, align 4
61146
%3 = alloca i32, align 4

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,8 +82,7 @@ body: |
8282
# CHECK: bb.0:
8383
# CHECK: frame-setup EMITBKEY
8484
# CHECK-NEXT: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp
85-
# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state
86-
# CHECK-NEXT: frame-setup CFI_INSTRUCTION
85+
# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state
8786
# CHECK-NOT: OUTLINED_FUNCTION_
8887
# CHECK: bb.1:
8988
# CHECK-NOT: OUTLINED_FUNCTION_

‎llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll

Lines changed: 113 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,46 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
23
; RUN: FileCheck %s --check-prefixes CHECK,V8A
34
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
45
; RUN: FileCheck %s --check-prefixes CHECK,V83A
56

67
define void @a() "sign-return-address"="all" {
7-
; CHECK-LABEL: a: // @a
8-
; V8A: hint #25
9-
; V83A: paciasp
10-
; CHECK: .cfi_negate_ra_state
11-
; CHECK-NEXT: .cfi_def_cfa_offset
8+
; V8A-LABEL: a:
9+
; V8A: // %bb.0:
10+
; V8A-NEXT: hint #25
11+
; V8A-NEXT: .cfi_negate_ra_state
12+
; V8A-NEXT: sub sp, sp, #32
13+
; V8A-NEXT: .cfi_def_cfa_offset 32
14+
; V8A-NEXT: mov w8, #1 // =0x1
15+
; V8A-NEXT: mov w9, #2 // =0x2
16+
; V8A-NEXT: stp w9, w8, [sp, #24]
17+
; V8A-NEXT: mov w9, #3 // =0x3
18+
; V8A-NEXT: mov w8, #4 // =0x4
19+
; V8A-NEXT: stp w8, w9, [sp, #16]
20+
; V8A-NEXT: mov w9, #5 // =0x5
21+
; V8A-NEXT: mov w8, #6 // =0x6
22+
; V8A-NEXT: stp w8, w9, [sp, #8]
23+
; V8A-NEXT: add sp, sp, #32
24+
; V8A-NEXT: hint #29
25+
; V8A-NEXT: ret
26+
;
27+
; V83A-LABEL: a:
28+
; V83A: // %bb.0:
29+
; V83A-NEXT: paciasp
30+
; V83A-NEXT: .cfi_negate_ra_state
31+
; V83A-NEXT: sub sp, sp, #32
32+
; V83A-NEXT: .cfi_def_cfa_offset 32
33+
; V83A-NEXT: mov w8, #1 // =0x1
34+
; V83A-NEXT: mov w9, #2 // =0x2
35+
; V83A-NEXT: stp w9, w8, [sp, #24]
36+
; V83A-NEXT: mov w9, #3 // =0x3
37+
; V83A-NEXT: mov w8, #4 // =0x4
38+
; V83A-NEXT: stp w8, w9, [sp, #16]
39+
; V83A-NEXT: mov w9, #5 // =0x5
40+
; V83A-NEXT: mov w8, #6 // =0x6
41+
; V83A-NEXT: stp w8, w9, [sp, #8]
42+
; V83A-NEXT: add sp, sp, #32
43+
; V83A-NEXT: retaa
1244
%1 = alloca i32, align 4
1345
%2 = alloca i32, align 4
1446
%3 = alloca i32, align 4
@@ -21,19 +53,48 @@ define void @a() "sign-return-address"="all" {
2153
store i32 4, ptr %4, align 4
2254
store i32 5, ptr %5, align 4
2355
store i32 6, ptr %6, align 4
24-
; V8A: hint #29
25-
; V83A: retaa
2656
ret void
27-
; CHECK: .cfi_endproc
2857
}
2958

3059
define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
31-
; CHECK-LABEL: b: // @b
32-
; CHECK: .cfi_b_key_frame
33-
; V8A-NEXT: hint #27
34-
; V83A-NEXT: pacibsp
35-
; CHECK: .cfi_negate_ra_state
36-
; CHECK-NEXT: .cfi_def_cfa_offset
60+
; V8A-LABEL: b:
61+
; V8A: // %bb.0:
62+
; V8A-NEXT: .cfi_b_key_frame
63+
; V8A-NEXT: hint #27
64+
; V8A-NEXT: .cfi_negate_ra_state
65+
; V8A-NEXT: sub sp, sp, #32
66+
; V8A-NEXT: .cfi_def_cfa_offset 32
67+
; V8A-NEXT: mov w8, #1 // =0x1
68+
; V8A-NEXT: mov w9, #2 // =0x2
69+
; V8A-NEXT: stp w9, w8, [sp, #24]
70+
; V8A-NEXT: mov w9, #3 // =0x3
71+
; V8A-NEXT: mov w8, #4 // =0x4
72+
; V8A-NEXT: stp w8, w9, [sp, #16]
73+
; V8A-NEXT: mov w9, #5 // =0x5
74+
; V8A-NEXT: mov w8, #6 // =0x6
75+
; V8A-NEXT: stp w8, w9, [sp, #8]
76+
; V8A-NEXT: add sp, sp, #32
77+
; V8A-NEXT: hint #31
78+
; V8A-NEXT: ret
79+
;
80+
; V83A-LABEL: b:
81+
; V83A: // %bb.0:
82+
; V83A-NEXT: .cfi_b_key_frame
83+
; V83A-NEXT: pacibsp
84+
; V83A-NEXT: .cfi_negate_ra_state
85+
; V83A-NEXT: sub sp, sp, #32
86+
; V83A-NEXT: .cfi_def_cfa_offset 32
87+
; V83A-NEXT: mov w8, #1 // =0x1
88+
; V83A-NEXT: mov w9, #2 // =0x2
89+
; V83A-NEXT: stp w9, w8, [sp, #24]
90+
; V83A-NEXT: mov w9, #3 // =0x3
91+
; V83A-NEXT: mov w8, #4 // =0x4
92+
; V83A-NEXT: stp w8, w9, [sp, #16]
93+
; V83A-NEXT: mov w9, #5 // =0x5
94+
; V83A-NEXT: mov w8, #6 // =0x6
95+
; V83A-NEXT: stp w8, w9, [sp, #8]
96+
; V83A-NEXT: add sp, sp, #32
97+
; V83A-NEXT: retab
3798
%1 = alloca i32, align 4
3899
%2 = alloca i32, align 4
39100
%3 = alloca i32, align 4
@@ -46,19 +107,46 @@ define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
46107
store i32 4, ptr %4, align 4
47108
store i32 5, ptr %5, align 4
48109
store i32 6, ptr %6, align 4
49-
; V8A-NOT: hint #29
50-
; V83A-NOT: autiasp
51-
; V83A-NOT: retaa
52110
ret void
53-
; CHECK: .cfi_endproc
54111
}
55112

56113
define void @c() "sign-return-address"="all" {
57-
; CHECK-LABEL: c: // @c
58-
; V8A: hint #25
59-
; V83A: paciasp
60-
; CHECK: .cfi_negate_ra_state
61-
; CHECK-NEXT: .cfi_def_cfa_offset
114+
; V8A-LABEL: c:
115+
; V8A: // %bb.0:
116+
; V8A-NEXT: hint #25
117+
; V8A-NEXT: .cfi_negate_ra_state
118+
; V8A-NEXT: sub sp, sp, #32
119+
; V8A-NEXT: .cfi_def_cfa_offset 32
120+
; V8A-NEXT: mov w8, #1 // =0x1
121+
; V8A-NEXT: mov w9, #2 // =0x2
122+
; V8A-NEXT: stp w9, w8, [sp, #24]
123+
; V8A-NEXT: mov w9, #3 // =0x3
124+
; V8A-NEXT: mov w8, #4 // =0x4
125+
; V8A-NEXT: stp w8, w9, [sp, #16]
126+
; V8A-NEXT: mov w9, #5 // =0x5
127+
; V8A-NEXT: mov w8, #6 // =0x6
128+
; V8A-NEXT: stp w8, w9, [sp, #8]
129+
; V8A-NEXT: add sp, sp, #32
130+
; V8A-NEXT: hint #29
131+
; V8A-NEXT: ret
132+
;
133+
; V83A-LABEL: c:
134+
; V83A: // %bb.0:
135+
; V83A-NEXT: paciasp
136+
; V83A-NEXT: .cfi_negate_ra_state
137+
; V83A-NEXT: sub sp, sp, #32
138+
; V83A-NEXT: .cfi_def_cfa_offset 32
139+
; V83A-NEXT: mov w8, #1 // =0x1
140+
; V83A-NEXT: mov w9, #2 // =0x2
141+
; V83A-NEXT: stp w9, w8, [sp, #24]
142+
; V83A-NEXT: mov w9, #3 // =0x3
143+
; V83A-NEXT: mov w8, #4 // =0x4
144+
; V83A-NEXT: stp w8, w9, [sp, #16]
145+
; V83A-NEXT: mov w9, #5 // =0x5
146+
; V83A-NEXT: mov w8, #6 // =0x6
147+
; V83A-NEXT: stp w8, w9, [sp, #8]
148+
; V83A-NEXT: add sp, sp, #32
149+
; V83A-NEXT: retaa
62150
%1 = alloca i32, align 4
63151
%2 = alloca i32, align 4
64152
%3 = alloca i32, align 4
@@ -71,11 +159,10 @@ define void @c() "sign-return-address"="all" {
71159
store i32 4, ptr %4, align 4
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store i32 5, ptr %5, align 4
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store i32 6, ptr %6, align 4
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; V8A: hint #29
75-
; V83A: retaa
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ret void
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; CHECK: .cfi_endproc
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}
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; CHECK-NOT: OUTLINED_FUNCTION_0:
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; CHECK-NOT: // -- Begin function
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

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