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Sumanth Gundapaneni
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[Hexagon] Generate absolute-set load/store instructions. (#82034)
The optimization finds the loads/stores of a specific form and translate the first load/store to an absolute-set form there by optimizing out the transfer and eliminate the constant extenders.
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‎llvm/lib/Target/Hexagon/CMakeLists.txt

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@@ -33,6 +33,7 @@ add_llvm_target(HexagonCodeGen
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HexagonFrameLowering.cpp
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HexagonGenExtract.cpp
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HexagonGenInsert.cpp
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HexagonGenMemAbsolute.cpp
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HexagonGenMux.cpp
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HexagonGenPredicate.cpp
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HexagonHardwareLoops.cpp

‎llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp

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//===--- HexagonGenMemAbsolute.cpp - Generate Load/Store Set Absolute ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This pass traverses through all the basic blocks in a function and converts
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// an indexed load/store with offset "0" to a absolute-set load/store
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// instruction as long as the use of the register in the new instruction
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// dominates the rest of the uses and there are more than 2 uses.
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "hexagon-abs"
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using namespace llvm;
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STATISTIC(HexagonNumLoadAbsConversions,
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"Number of Load instructions converted to absolute-set form");
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STATISTIC(HexagonNumStoreAbsConversions,
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"Number of Store instructions converted to absolute-set form");
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namespace llvm {
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FunctionPass *createHexagonGenMemAbsolute();
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void initializeHexagonGenMemAbsolutePass(PassRegistry &Registry);
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} // namespace llvm
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namespace {
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class HexagonGenMemAbsolute : public MachineFunctionPass {
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const HexagonInstrInfo *TII;
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MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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public:
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static char ID;
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HexagonGenMemAbsolute() : MachineFunctionPass(ID), TII(0), MRI(0), TRI(0) {
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initializeHexagonGenMemAbsolutePass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override {
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return "Hexagon Generate Load/Store Set Absolute Address Instruction";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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private:
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static bool isValidIndexedLoad(int &Opcode, int &NewOpcode);
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static bool isValidIndexedStore(int &Opcode, int &NewOpcode);
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};
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} // namespace
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char HexagonGenMemAbsolute::ID = 0;
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INITIALIZE_PASS(HexagonGenMemAbsolute, "hexagon-gen-load-absolute",
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"Hexagon Generate Load/Store Set Absolute Address Instruction",
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false, false)
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bool HexagonGenMemAbsolute::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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TII = Fn.getSubtarget<HexagonSubtarget>().getInstrInfo();
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MRI = &Fn.getRegInfo();
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TRI = Fn.getRegInfo().getTargetRegisterInfo();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock *MBB = &*MBBb;
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// Traverse the basic block
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for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
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++MII) {
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MachineInstr *MI = &*MII;
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int Opc = MI->getOpcode();
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if (Opc != Hexagon::CONST32 && Opc != Hexagon::A2_tfrsi)
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continue;
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const MachineOperand &MO = MI->getOperand(0);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned DstReg = MO.getReg();
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if (MRI->use_nodbg_empty(DstReg))
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continue;
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typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
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use_iterator NextUseMI = MRI->use_nodbg_begin(DstReg);
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MachineInstr *NextMI = NextUseMI->getParent();
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int NextOpc = NextMI->getOpcode();
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int NewOpc;
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bool IsLoad = isValidIndexedLoad(NextOpc, NewOpc);
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if (!IsLoad && !isValidIndexedStore(NextOpc, NewOpc))
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continue;
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// Base and Offset positions for load and store instructions
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// Load R(dest), R(base), Imm -> R(dest) = mem(R(base) + Imm)
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// Store R(base), Imm, R (src) -> mem(R(base) + Imm) = R(src)
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unsigned BaseRegPos, ImmPos, RegPos;
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if (!TII->getBaseAndOffsetPosition(*NextMI, BaseRegPos, ImmPos))
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continue;
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RegPos = IsLoad ? 0 : 2;
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bool IsGlobal = MI->getOperand(1).isGlobal();
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if (!MI->getOperand(1).isImm() && !IsGlobal)
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continue;
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const MachineOperand *BaseOp = nullptr;
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int64_t Offset;
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bool Scalable;
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TII->getMemOperandWithOffset(*NextMI, BaseOp, Offset, Scalable, TRI);
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// Ensure BaseOp is non-null and register type.
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if (!BaseOp || !BaseOp->isReg())
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continue;
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if (Scalable)
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continue;
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unsigned BaseReg = BaseOp->getReg();
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if ((DstReg != BaseReg) || (Offset != 0))
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continue;
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const MachineOperand &MO0 = NextMI->getOperand(RegPos);
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if (!MO0.isReg())
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continue;
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unsigned LoadStoreReg = MO0.getReg();
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// Store: Bail out if the src and base are same (def and use on same
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// register).
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if (LoadStoreReg == BaseReg)
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continue;
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// Insert the absolute-set instruction "I" only if the use of the
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// BaseReg in "I" dominates the rest of the uses of BaseReg and if
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// there are more than 2 uses of this BaseReg.
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bool Dominates = true;
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unsigned Counter = 0;
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for (use_iterator I = NextUseMI, E = MRI->use_nodbg_end(); I != E; ++I) {
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Counter++;
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if (!MDT.dominates(NextMI, I->getParent()))
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Dominates = false;
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}
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if ((!Dominates) || (Counter < 3))
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continue;
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// If we reach here, we have met all the conditions required for the
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// replacement of the absolute instruction.
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LLVM_DEBUG({
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dbgs() << "Found a pair of instructions for absolute-set "
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<< (IsLoad ? "load" : "store") << "\n";
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dbgs() << *MI;
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dbgs() << *NextMI;
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});
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MachineBasicBlock *ParentBlock = NextMI->getParent();
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MachineInstrBuilder MIB;
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if (IsLoad) { // Insert absolute-set load instruction
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++HexagonNumLoadAbsConversions;
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MIB = BuildMI(*ParentBlock, NextMI, NextMI->getDebugLoc(),
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TII->get(NewOpc), LoadStoreReg)
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.addReg(DstReg, RegState::Define);
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} else { // Insert absolute-set store instruction
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++HexagonNumStoreAbsConversions;
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MIB = BuildMI(*ParentBlock, NextMI, NextMI->getDebugLoc(),
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TII->get(NewOpc), DstReg);
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}
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MachineOperand ImmOperand = MI->getOperand(1);
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if (IsGlobal)
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MIB.addGlobalAddress(ImmOperand.getGlobal(), ImmOperand.getOffset(),
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ImmOperand.getTargetFlags());
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else
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MIB.addImm(ImmOperand.getImm());
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if (IsLoad)
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MIB->getOperand(0).setSubReg(MO0.getSubReg());
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else
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MIB.addReg(LoadStoreReg, 0, MO0.getSubReg());
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LLVM_DEBUG(dbgs() << "Replaced with " << *MIB << "\n");
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// Erase the instructions that got replaced.
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MII = MBB->erase(MI);
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--MII;
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NextMI->getParent()->erase(NextMI);
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}
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}
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return true;
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}
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bool HexagonGenMemAbsolute::isValidIndexedLoad(int &Opc, int &NewOpc) {
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bool Result = true;
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switch (Opc) {
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case Hexagon::L2_loadrb_io:
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NewOpc = Hexagon::L4_loadrb_ap;
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break;
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case Hexagon::L2_loadrh_io:
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NewOpc = Hexagon::L4_loadrh_ap;
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break;
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case Hexagon::L2_loadri_io:
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NewOpc = Hexagon::L4_loadri_ap;
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break;
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case Hexagon::L2_loadrd_io:
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NewOpc = Hexagon::L4_loadrd_ap;
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break;
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case Hexagon::L2_loadruh_io:
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NewOpc = Hexagon::L4_loadruh_ap;
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break;
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case Hexagon::L2_loadrub_io:
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NewOpc = Hexagon::L4_loadrub_ap;
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break;
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default:
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Result = false;
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}
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return Result;
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}
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bool HexagonGenMemAbsolute::isValidIndexedStore(int &Opc, int &NewOpc) {
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bool Result = true;
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switch (Opc) {
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case Hexagon::S2_storerd_io:
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NewOpc = Hexagon::S4_storerd_ap;
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break;
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case Hexagon::S2_storeri_io:
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NewOpc = Hexagon::S4_storeri_ap;
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break;
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case Hexagon::S2_storerh_io:
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NewOpc = Hexagon::S4_storerh_ap;
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break;
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case Hexagon::S2_storerb_io:
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NewOpc = Hexagon::S4_storerb_ap;
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break;
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default:
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Result = false;
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}
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return Result;
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *llvm::createHexagonGenMemAbsolute() {
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return new HexagonGenMemAbsolute();
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}

‎llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

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@@ -92,6 +92,10 @@ static cl::opt<bool>
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static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
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cl::desc("Disable splitting double registers"));
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static cl::opt<bool>
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EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden,
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cl::desc("Generate absolute set instructions"));
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static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
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cl::Hidden, cl::desc("Bit simplification"));
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void initializeHexagonCopyToCombinePass(PassRegistry&);
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void initializeHexagonEarlyIfConversionPass(PassRegistry&);
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void initializeHexagonExpandCondsetsPass(PassRegistry&);
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void initializeHexagonGenMemAbsolutePass(PassRegistry &);
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void initializeHexagonGenMuxPass(PassRegistry&);
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void initializeHexagonHardwareLoopsPass(PassRegistry&);
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void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonGenExtract();
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FunctionPass *createHexagonGenInsert();
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FunctionPass *createHexagonGenMemAbsolute();
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FunctionPass *createHexagonGenMux();
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FunctionPass *createHexagonGenPredicate();
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FunctionPass *createHexagonHardwareLoops();
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initializeHexagonConstPropagationPass(PR);
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initializeHexagonCopyToCombinePass(PR);
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initializeHexagonEarlyIfConversionPass(PR);
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initializeHexagonGenMemAbsolutePass(PR);
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initializeHexagonGenMuxPass(PR);
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initializeHexagonHardwareLoopsPass(PR);
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initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
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insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
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if (!DisableStoreWidening)
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addPass(createHexagonStoreWidening());
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if (EnableGenMemAbs)
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addPass(createHexagonGenMemAbsolute());
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops());
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}

‎llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll

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; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s
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; This test checks the case if there are more than 2 uses of a constan address, move the
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; value in to a register and replace all instances of constant with the register.
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; The GenMemAbsolute pass generates a absolute-set instruction if there are more
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; than 2 uses of this register.
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; CHECK: loadi32_3
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
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; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##441652)
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; CHECK-NOT: r{{[0-9]+}} = {emw(##441652)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##441652)
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define void @loadi32_3() #0 {
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entry:
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%0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%2 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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ret void
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}
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; CHECK: loadi32_2
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; CHECK-NOT: r{{[0-9]+}} = ##441652
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; CHECK: r{{[0-9]+}} = memw(##441652)
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; CHECK: r{{[0-9]+}} = memw(##441652)
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define void @loadi32_2() #0 {
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entry:
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%0 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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%1 = load volatile i32, ptr inttoptr (i32 441652 to ptr), align 4
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ret void
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}
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; CHECK: loadi32_abs_global_3
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
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; CHECK:r{{[0-9]+}} = memw(r[[REG:[0-9]+]]=##globalInt)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(r[[REG]]+#0)
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; CHECK-NOT: r{{[0-9]+}} = memw(##globalInt)
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@globalInt = external global i32, align 8
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define void @loadi32_abs_global_3() #0 {
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entry:
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%0 = load volatile i32, ptr @globalInt, align 4
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%1 = load volatile i32, ptr @globalInt, align 4
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%2 = load volatile i32, ptr @globalInt, align 4
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ret void
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}
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; CHECK: loadi32_abs_global_2
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; CHECK-NOT:r[[REG:[0-9]+]] = ##globalInt
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; CHECK:r{{[0-9]+}} = memw(##globalInt)
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; CHECK:r{{[0-9]+}} = memw(##globalInt)
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define void @loadi32_abs_global_2() #0 {
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entry:
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%0 = load volatile i32, ptr @globalInt, align 4
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%1 = load volatile i32, ptr @globalInt, align 4
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ret void
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}
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attributes #0 = { nounwind }

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