[RISCV] Use COPY to create artificial 64-bit uses in RISCVOptWInstrs's tests

In reflection of 4dd5d96, we can now
use COPY to physical registers to create artificial 64-bit uses to
prevent RISCVOptWInstrs from optimizing away sext in absent of the
IsSignExtendingOpW flag.

NFCI.

Author: mshockwave

llvm/test/CodeGen/RISCV/opt-w-instrs.mir

@@ -6,26 +6,20 @@ name:            fcvtmod_w_d
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
-    liveins: $x10, $x11
+    liveins: $x10
 
     ; CHECK-ZFA-LABEL: name: fcvtmod_w_d
-    ; CHECK-ZFA: liveins: $x10, $x11
+    ; CHECK-ZFA: liveins: $x10
     ; CHECK-ZFA-NEXT: {{  $}}
     ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
-    ; CHECK-ZFA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
     ; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
-    ; CHECK-ZFA-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[FCVTMOD_W_D]]
-    ; CHECK-ZFA-NEXT: $x10 = COPY [[ADD]]
-    ; CHECK-ZFA-NEXT: $x11 = COPY [[FCVTMOD_W_D]]
+    ; CHECK-ZFA-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
     ; CHECK-ZFA-NEXT: PseudoRET
     %0:fpr64 = COPY $x10
-    %1:gpr = COPY $x11
 
-    %2:gpr = nofpexcept FCVTMOD_W_D %0, 1
-    %3:gpr = ADD %1, %2
-    %4:gpr = ADDIW %2, 0
-    $x10 = COPY %3
-    $x11 = COPY %4
+    %1:gpr = nofpexcept FCVTMOD_W_D %0, 1
+    %2:gpr = ADDIW %1, 0
+    $x10 = COPY %2
     PseudoRET
 ...