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michaelmaitlandmichaelmaitland
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[RISCV] Model integer min max instructions from Zbb execute in late-B ALU
We don't model the early vs late ALU so we just need to remove usage of SiFivePipeA for these instructions.
1 parent 04d9b98 commit 4c7a681

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3 files changed

+21
-20
lines changed

3 files changed

+21
-20
lines changed

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -305,7 +305,8 @@ def : WriteRes<WriteCPOP32, [SiFive7PipeB]>;
305305
// orc.b is in the late-B ALU.
306306
def : WriteRes<WriteORCB, [SiFive7PipeB]>;
307307

308-
def : WriteRes<WriteIMinMax, [SiFive7PipeAB]>;
308+
// min/max are in the late-B ALU
309+
def : WriteRes<WriteIMinMax, [SiFive7PipeB]>;
309310

310311
// rev8 is in the late-A and late-B ALUs.
311312
def : WriteRes<WriteREV8, [SiFive7PipeAB]>;

‎llvm/test/CodeGen/RISCV/machine-combiner.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -740,9 +740,9 @@ define i8 @test_reassoc_minu_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
740740
; CHECK-LABEL: test_reassoc_minu_i8:
741741
; CHECK: # %bb.0:
742742
; CHECK-NEXT: andi a3, a3, 255
743-
; CHECK-NEXT: andi a2, a2, 255
744743
; CHECK-NEXT: andi a1, a1, 255
745744
; CHECK-NEXT: andi a0, a0, 255
745+
; CHECK-NEXT: andi a2, a2, 255
746746
; CHECK-NEXT: minu a0, a0, a1
747747
; CHECK-NEXT: minu a1, a2, a3
748748
; CHECK-NEXT: minu a0, a0, a1
@@ -757,9 +757,9 @@ define i16 @test_reassoc_minu_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
757757
; CHECK-LABEL: test_reassoc_minu_i16:
758758
; CHECK: # %bb.0:
759759
; CHECK-NEXT: zext.h a3, a3
760-
; CHECK-NEXT: zext.h a2, a2
761760
; CHECK-NEXT: zext.h a1, a1
762761
; CHECK-NEXT: zext.h a0, a0
762+
; CHECK-NEXT: zext.h a2, a2
763763
; CHECK-NEXT: minu a0, a0, a1
764764
; CHECK-NEXT: minu a1, a2, a3
765765
; CHECK-NEXT: minu a0, a0, a1
@@ -774,9 +774,9 @@ define i32 @test_reassoc_minu_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
774774
; CHECK-LABEL: test_reassoc_minu_i32:
775775
; CHECK: # %bb.0:
776776
; CHECK-NEXT: sext.w a3, a3
777-
; CHECK-NEXT: sext.w a2, a2
778777
; CHECK-NEXT: sext.w a1, a1
779778
; CHECK-NEXT: sext.w a0, a0
779+
; CHECK-NEXT: sext.w a2, a2
780780
; CHECK-NEXT: minu a0, a0, a1
781781
; CHECK-NEXT: minu a1, a2, a3
782782
; CHECK-NEXT: minu a0, a0, a1
@@ -804,9 +804,9 @@ define i8 @test_reassoc_min_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
804804
; CHECK-LABEL: test_reassoc_min_i8:
805805
; CHECK: # %bb.0:
806806
; CHECK-NEXT: sext.b a3, a3
807-
; CHECK-NEXT: sext.b a2, a2
808807
; CHECK-NEXT: sext.b a1, a1
809808
; CHECK-NEXT: sext.b a0, a0
809+
; CHECK-NEXT: sext.b a2, a2
810810
; CHECK-NEXT: min a0, a0, a1
811811
; CHECK-NEXT: min a1, a2, a3
812812
; CHECK-NEXT: min a0, a0, a1
@@ -821,9 +821,9 @@ define i16 @test_reassoc_min_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
821821
; CHECK-LABEL: test_reassoc_min_i16:
822822
; CHECK: # %bb.0:
823823
; CHECK-NEXT: sext.h a3, a3
824-
; CHECK-NEXT: sext.h a2, a2
825824
; CHECK-NEXT: sext.h a1, a1
826825
; CHECK-NEXT: sext.h a0, a0
826+
; CHECK-NEXT: sext.h a2, a2
827827
; CHECK-NEXT: min a0, a0, a1
828828
; CHECK-NEXT: min a1, a2, a3
829829
; CHECK-NEXT: min a0, a0, a1
@@ -838,9 +838,9 @@ define i32 @test_reassoc_min_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
838838
; CHECK-LABEL: test_reassoc_min_i32:
839839
; CHECK: # %bb.0:
840840
; CHECK-NEXT: sext.w a3, a3
841-
; CHECK-NEXT: sext.w a2, a2
842841
; CHECK-NEXT: sext.w a1, a1
843842
; CHECK-NEXT: sext.w a0, a0
843+
; CHECK-NEXT: sext.w a2, a2
844844
; CHECK-NEXT: min a0, a0, a1
845845
; CHECK-NEXT: min a1, a2, a3
846846
; CHECK-NEXT: min a0, a0, a1
@@ -868,9 +868,9 @@ define i8 @test_reassoc_maxu_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
868868
; CHECK-LABEL: test_reassoc_maxu_i8:
869869
; CHECK: # %bb.0:
870870
; CHECK-NEXT: andi a3, a3, 255
871-
; CHECK-NEXT: andi a2, a2, 255
872871
; CHECK-NEXT: andi a1, a1, 255
873872
; CHECK-NEXT: andi a0, a0, 255
873+
; CHECK-NEXT: andi a2, a2, 255
874874
; CHECK-NEXT: maxu a0, a0, a1
875875
; CHECK-NEXT: maxu a1, a2, a3
876876
; CHECK-NEXT: maxu a0, a0, a1
@@ -885,9 +885,9 @@ define i16 @test_reassoc_maxu_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
885885
; CHECK-LABEL: test_reassoc_maxu_i16:
886886
; CHECK: # %bb.0:
887887
; CHECK-NEXT: zext.h a3, a3
888-
; CHECK-NEXT: zext.h a2, a2
889888
; CHECK-NEXT: zext.h a1, a1
890889
; CHECK-NEXT: zext.h a0, a0
890+
; CHECK-NEXT: zext.h a2, a2
891891
; CHECK-NEXT: maxu a0, a0, a1
892892
; CHECK-NEXT: maxu a1, a2, a3
893893
; CHECK-NEXT: maxu a0, a0, a1
@@ -902,9 +902,9 @@ define i32 @test_reassoc_maxu_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
902902
; CHECK-LABEL: test_reassoc_maxu_i32:
903903
; CHECK: # %bb.0:
904904
; CHECK-NEXT: sext.w a3, a3
905-
; CHECK-NEXT: sext.w a2, a2
906905
; CHECK-NEXT: sext.w a1, a1
907906
; CHECK-NEXT: sext.w a0, a0
907+
; CHECK-NEXT: sext.w a2, a2
908908
; CHECK-NEXT: maxu a0, a0, a1
909909
; CHECK-NEXT: maxu a1, a2, a3
910910
; CHECK-NEXT: maxu a0, a0, a1
@@ -932,9 +932,9 @@ define i8 @test_reassoc_max_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
932932
; CHECK-LABEL: test_reassoc_max_i8:
933933
; CHECK: # %bb.0:
934934
; CHECK-NEXT: sext.b a3, a3
935-
; CHECK-NEXT: sext.b a2, a2
936935
; CHECK-NEXT: sext.b a1, a1
937936
; CHECK-NEXT: sext.b a0, a0
937+
; CHECK-NEXT: sext.b a2, a2
938938
; CHECK-NEXT: max a0, a0, a1
939939
; CHECK-NEXT: max a1, a2, a3
940940
; CHECK-NEXT: max a0, a0, a1
@@ -949,9 +949,9 @@ define i16 @test_reassoc_max_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
949949
; CHECK-LABEL: test_reassoc_max_i16:
950950
; CHECK: # %bb.0:
951951
; CHECK-NEXT: sext.h a3, a3
952-
; CHECK-NEXT: sext.h a2, a2
953952
; CHECK-NEXT: sext.h a1, a1
954953
; CHECK-NEXT: sext.h a0, a0
954+
; CHECK-NEXT: sext.h a2, a2
955955
; CHECK-NEXT: max a0, a0, a1
956956
; CHECK-NEXT: max a1, a2, a3
957957
; CHECK-NEXT: max a0, a0, a1
@@ -966,9 +966,9 @@ define i32 @test_reassoc_max_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
966966
; CHECK-LABEL: test_reassoc_max_i32:
967967
; CHECK: # %bb.0:
968968
; CHECK-NEXT: sext.w a3, a3
969-
; CHECK-NEXT: sext.w a2, a2
970969
; CHECK-NEXT: sext.w a1, a1
971970
; CHECK-NEXT: sext.w a0, a0
971+
; CHECK-NEXT: sext.w a2, a2
972972
; CHECK-NEXT: max a0, a0, a1
973973
; CHECK-NEXT: max a1, a2, a3
974974
; CHECK-NEXT: max a0, a0, a1

‎llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -180,10 +180,10 @@ jr a0
180180
# CHECK-NEXT: 1 3 0.50 sext.b a0, a0
181181
# CHECK-NEXT: 1 3 0.50 sext.h a0, a0
182182
# CHECK-NEXT: 1 3 0.50 zext.h a0, a0
183-
# CHECK-NEXT: 1 3 0.50 min a0, a0, a0
184-
# CHECK-NEXT: 1 3 0.50 minu a0, a0, a0
185-
# CHECK-NEXT: 1 3 0.50 max a0, a0, a0
186-
# CHECK-NEXT: 1 3 0.50 maxu a0, a0, a0
183+
# CHECK-NEXT: 1 3 1.00 min a0, a0, a0
184+
# CHECK-NEXT: 1 3 1.00 minu a0, a0, a0
185+
# CHECK-NEXT: 1 3 1.00 max a0, a0, a0
186+
# CHECK-NEXT: 1 3 1.00 maxu a0, a0, a0
187187
# CHECK-NEXT: 1 3 1.00 rol a0, a0, a0
188188
# CHECK-NEXT: 1 3 1.00 ror a0, a0, a0
189189
# CHECK-NEXT: 1 3 1.00 rori a0, a0, 1
@@ -225,7 +225,7 @@ jr a0
225225

226226
# CHECK: Resource pressure per iteration:
227227
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
228-
# CHECK-NEXT: - - 39.00 52.00 - - - -
228+
# CHECK-NEXT: - - 37.00 54.00 - - - -
229229

230230
# CHECK: Resource pressure by instruction:
231231
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -289,9 +289,9 @@ jr a0
289289
# CHECK-NEXT: - - - 1.00 - - - - sext.h a0, a0
290290
# CHECK-NEXT: - - 1.00 - - - - - zext.h a0, a0
291291
# CHECK-NEXT: - - - 1.00 - - - - min a0, a0, a0
292-
# CHECK-NEXT: - - 1.00 - - - - - minu a0, a0, a0
292+
# CHECK-NEXT: - - - 1.00 - - - - minu a0, a0, a0
293293
# CHECK-NEXT: - - - 1.00 - - - - max a0, a0, a0
294-
# CHECK-NEXT: - - 1.00 - - - - - maxu a0, a0, a0
294+
# CHECK-NEXT: - - - 1.00 - - - - maxu a0, a0, a0
295295
# CHECK-NEXT: - - - 1.00 - - - - rol a0, a0, a0
296296
# CHECK-NEXT: - - - 1.00 - - - - ror a0, a0, a0
297297
# CHECK-NEXT: - - - 1.00 - - - - rori a0, a0, 1

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